Abstract: A semiconductor memory device includes a memory cell array including a plurality of wordlines, a plurality of bitlines and a plurality of cells; a bitline decoder configured to couple a global bitline to one of the plurality of bitlines according to a bitline selection signal; a bitline driver configured to provide bitline current to the global bitline; a wordline decoder configured to couple a global wordline to one of the plurality of wordlines according to a wordline selection signal; a wordline driver configured to provide a wordline drive voltage to the global wordline during a write operation and to adjust the wordline drive voltage according to a write address; and a write control circuit configured to generate the wordline selection signal and the bitline selection signal, and to control the bitline decoder, the wordline decoder, and the bitline driver.

Abstract: An analog-to-digital converter (ADC) includes a first operator configured to subtract an analog value from an analog signal; an amplifier configured to amplify an output of the first selector; a filter configured to filter an output of the amplifier; a quantizer configured to generate a digital bit stream from an output of the filter; and a digital-to-analog converter (DAC) configured to output the analog value according to the digital bit stream.

Abstract: A capacitor includes a first electrode and a second electrode spaced apart from each other, a dielectric layer disposed between the first electrode and the second electrode, and a seed layer disposed between the first electrode and the dielectric layer. The dielectric layer includes a dielectric material having a tetragonal crystal structure. The seed layer includes a seed material that satisfies at least one of a lattice constant condition or a bond length condition.

Abstract: An analog-to-digital converter (ADC) includes an input circuit configured to receive a first analog signal output from a first sensor or a second analog signal output from a second sensor according to an operation mode and a bit stream; a filter configured to filter an output signal from the input circuit; a quantization circuit configured to generate the bit stream from an output signal of the filter; and a digital circuit configured to generate a first digital signal corresponding to the first analog signal or a second digital signal corresponding to the second analog signal by filtering the bit stream, wherein the operation mode includes a first mode selecting the first sensor and a second mode selecting the second sensor, and wherein the digital circuit refers to the second digital signal generated during the second mode to generate the first digital signal during the first mode.

Abstract: Disclosed is a sound data processing system including a plurality of sound collecting terminals and a server. Each of the plurality of sound collecting terminals includes: a sound collecting means that collects a sound and has an orientation direction, and a communication module that transmits sound data corresponding to the sound collected by the sound collecting means and supplementary data including position data of a position of a corresponding sound collecting terminal and orientation direction data corresponding to the orientation direction of the sound collecting means via a network. The server receives the sound data and the supplementary data transmitted by the plurality of sound collecting terminals through the network and determines a position of a source that emits the sound collected by the sound collecting means on the basis of the sound data and the supplementary data.

Abstract: The present invention relates to a composition for treating osteoarthritis and a method for preparing the same, and more specifically, relates to a composition comprising hydrophilized sulfasalazine as an active ingredient and hyaluronic acid so as to enable effective treatment of osteoarthritis such as degenerative osteoarthritis by preventing joint wear in addition to symptom relief through intraarticular or local administration, and a method for preparing the same.

Abstract: Apparatuses, methods and storage medium associated with deriving power output from an energy harvester are disclosed herein. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to identify a plurality of times at which an intermediate voltage of a two stage power conversion circuit corresponds to a voltage reference, and ascertain an amount of time between one of the identified times and another one of the identified times. The one or more processors, devices, and/or circuitry may derive a power or current value associated with the second power supply using the amount of time.

Abstract: A semiconductor device includes a control voltage generator to generate a control voltage according to a temperature section signal; and a temperature voltage output block to output a temperature voltage varying with a temperature according to the control voltage and the temperature section signal.

Abstract: A data receiving circuit may include: a variable delay circuit suitable for generating a delayed strobe signal by delaying a strobe signal; a receiving circuit suitable for sampling data in synchronization with the delayed strobe signal; a phase shift circuit suitable for generating a shifted strobe signal by shifting a phase of the delayed strobe signal; a phase comparison circuit suitable for comparing phases of the data and the shifted strobe signal; and a delay adjusting circuit suitable for adjusting a delay value of the variable delay circuit in response to the phase comparison result of the phase comparison circuit.

Abstract: A microelectromechanical sensors (MEMS) device includes a MEMS transducer attached on a substrate; a semiconductor chip attached on the substrate and electrically connected to the MEMS transducer; and a case attached on the substrate so that the MEMS transducer and the semiconductor chip be covered, wherein the substrate includes a first passage formed below the MEMS transducer, wherein the case includes a second passage, and wherein the MEMS transducer includes a diaphragm having a third passage formed therein.

Abstract: A microelectromechanical sensors (MEMS) device includes a first substrate, a MEMS transducer package attached on the first substrate and including a MEMS transducer therein configured to output an electrical signal corresponding to movement of fluid, and a semiconductor device attached on the first substrate and configured to process the electrical signal provided from the MEMS transducer.

Abstract: An image information collecting system comprises: a position transmitting device for transmitting first position information indicating a position of the image information collecting system itself; a plurality of cameras for collecting image data, storing the image data in a storage medium of the image information collecting system itself, generating data identification including oriented direction information of a camera and time information at a time point at which the image data has been collected, and transmitting the data identification information through a network; and a service server for receiving the first position information and the data identification information, and determining whether a target camera for photographing a current position of the position transmitting device exists among the plurality of cameras, using the data identification information and second position information indicating positions of the plurality of cameras.

Abstract: In an embodiment, a unit delay circuit comprises a first path configured to delay a first input signal to output a first output signal when a selection signal is inactivated, a second path configured delay a second input signal to output a second output signal when the selection signal is inactivated, and a third path configured to delay the first input signal to output the second output signal when the selection signal is activated.

Abstract: A sound data processing system includes a plurality of sound collecting terminals and a server, wherein each of the plurality of sound collecting terminals and each of the plurality of sound providing terminals includes a sound collecting means that collects a sound while having a position and an orientation direction, a sound providing means that provides a sound while having an orientation direction, a position detecting means that detects the positions of the sound collecting means and the sound providing means, a direction detecting means that detects the orientation directions, and a communication module that transmits sound data corresponding to the sound collected by the sound collecting means and supplementary data including position data corresponding to the position detected by the position detecting means and orientation direction data corresponding to the orientation direction detected by the direction detecting means and through a network.

Abstract: A data receiver circuit may include: a delay circuit suitable for delaying first and second strobe signals and generating delayed first and second strobe signals; a first receiver circuit suitable for sampling data in synchronization with the delayed first strobe signal; a second receiver circuit suitable for sampling the data in synchronization with the delayed second strobe signal; an enable signal generation circuit suitable for generating an enable signal indicating whether the data transitioned; a transition level generation circuit suitable for generating a transition level signal indicating a transition direction of the data; a phase shift circuit suitable for shifting the phase of the delayed first strobe signal by a set degree and generating a shifted first strobe signal; a sampling circuit suitable for sampling the data in synchronization with the shifted first strobe signal and generating a sampling result; and a control logic suitable for changing a delay value of the delay circuit in response to

Abstract: A capacitor includes a first electrode and a second electrode spaced apart from each other, a dielectric layer disposed between the first electrode and the second electrode, and a seed layer disposed between the first electrode and the dielectric layer. The dielectric layer includes a dielectric material having a tetragonal crystal structure. The seed layer includes a seed material that satisfies at least one of a lattice constant condition or a bond length condition.

Abstract: Embodiments described herein concern operating a peak-delivered-power (PDP) controller. Operating a PDP includes calculating the new power output value from the output voltage value and the output current value, determining whether the new power output value is greater than the previous power output value to determine whether the voltage regulator is outputting a maximum power output, based on a determination that the new power output value is greater than the previous power output value, providing an instruction to a duty generator to increase a duty cycle of the voltage regulator, based on a determination that the new power output value is not greater than the previous power output value, providing an instruction to the duty generator to decrease the duty cycle of the voltage regulator, and replacing the previous power output value with the new power output value.

Abstract: An analog-to-digital converter (ADC) includes a modulator configured to oversample an input signal generated from an output signal of a transducer; and a filter configured to perform a decimation operation on an output from the modulator and a frequency characteristics correction operation according to a filter control signal on the output from the modulator, wherein the frequency characteristics correction operation is performed to complement a frequency characteristics of the output signal of the transducer such that overall frequency characteristics of the transducer and the filter be flat in a signal band.

Abstract: In an embodiment, a duty cycle controller comprises a delay circuit configured to output the feedback clock signal by delaying an output clock signal combined from an input clock signal and a feedback clock signal by a predetermined delay time, wherein the delay circuit comprises a unit delay circuit configured to delay the output clock signal by a time less than the predetermined delay time and configured to delay the feedback clock signal by the predetermined delay time by letting the output clock signal pass the unit delay circuit as many as a predetermined loop count.

Abstract: A capacitor includes a first electrode and a second electrode spaced apart from each other, a dielectric layer disposed between the first electrode and the second electrode, and a seed layer disposed between the first electrode and the dielectric layer. The dielectric layer includes a dielectric material having a tetragonal crystal structure. The seed layer includes a seed material that satisfies at least one of a lattice constant condition or a bond length condition.