Abstract: In one aspect, the invention includes a method of forming a silicon dioxide layer, including: a) forming a high density plasma proximate a substrate, the plasma including silicon dioxide precursors; b) forming silicon dioxide from the precursors, the silicon dioxide being deposited over the substrate at a deposition rate; and c) while depositing, etching the deposited silicon dioxide with the plasma at an etch rate; a ratio of the deposition rate to the etch rate being at least about 4:1. In another aspect, the invention includes a method of forming a silicon dioxide layer, including: a) forming a high density plasma proximate a substrate; b) flowing gases into the plasma, at least some of the gases forming silicon dioxide; c) depositing the silicon dioxide formed from the gases over the substrate; and d) while depositing the silicon dioxide, maintaining a temperature of the substrate at greater than or equal to about 500° C.

Abstract: Integrated circuits are generally built layer by layer on a substrate. One technique for forming layers is chemical vapor deposition (CVD.) This technique injects gases through a gas-dispersion fixture, such as a showerhead, into a chamber. The gases react and blanket a substrate in the chamber with a layer of material. One method of promoting uniform layer thickness is to coat the gas-dispersion fixture with a uniform layer of the material before using the fixture for deposition on the substrate. However, conventional fixture-coating techniques yield uneven or poorly adherent coatings. Accordingly, the inventor devised new methods for coating these fixtures. One exemplary method heats a fixture to a temperature greater than its temperature during normal deposition and then passes one or more gases through the fixture to form a coating on it. The greater conditioning temperature improves evenness and adhesion of the fixture coating, which, in turn, produces higher quality layers in integrated circuits.

Abstract: A method for fabricating gate electrodes and gate interconnects with a protective silicon oxide or silicon nitride cap and spacer formed by high density plasma chemical vapor deposition (HDPCVD). Silicon oxide or silicon nitride is deposited in a reaction zone of a HDPCVD reactor while providing two or more selected substrate bias powers, source powers and/or selected gas mixtures to tailor the shape and thickness of the film for desired applications. In one embodiment, a low bias power of below 500 Watts is provided in a first stage HDPCVD and the bias power is then increased to between 500 and 3000 Watts for a second stage to produce a protective film having thin sidewall spacers for enhanced semiconductor device density and a relatively thick cap.

Abstract: The present invention is a process for plasma enhanced fabrication of conductive materials on a substrate comprising the steps of placing substrate in an inductively coupled (IC) plasma reaction chamber and maintaining the chamber under vacuum pressure while introducing at least a preselected reactant species gas, and optionally a carrier gas into the chamber for a preselected fabrication procedure on the substrate. A plasma is generated from the gas or gases within the chamber using a power source inductively coupled to the reaction chamber. After the consequent fabrication procedure the substrate is removed from the chamber; and any conductive material is in-situ removed from the inside of the chamber to remove any blocking of the inductive power couple to the reaction chamber.

Abstract: The invention includes a method of forming a conductive interconnect. An electrical node location is defined to be supported by a silicon-containing substrate. A silicide is formed in contact with the electrical node location. The silicide is formed by exposing the substrate to hydrogen, TiCl4 and plasma conditions to cause Ti from the TiCl4 to combine with silicon of the substrate to form TiSix. Conductively doped silicon material is formed over the silicide. The conductively doped silicon material is exposed to one or more temperatures of at least about 800° C. The silicide is also exposed to the temperatures of at least about 800° C.

Abstract: Diffusion barrier film layers and methods of manufacture and use are provided. The films comprise boron-doped TiCl4-based titanium nitride, and provide an improved diffusion barrier having good adhesive, electrical conductivity, and anti-diffusion properties. The films can be formed on a silicon substrate without an underlying contact layer such as TiSix, an improvement in the fabrication of contacts to shallow junctions and other miniature components of integrated circuits.

Abstract: A new process for depositing titanium metal layers via chemical vapor deposition is disclosed. The process provides deposited titanium layers having a high degree of conformality, even in trenches and contact openings having aspect ratios greater than 1:5.

Abstract: In one aspect, the invention includes a method of forming a, silicon dioxide layer, including: a) forming a high density plasma proximate a substrate, the plasma including silicon dioxide precursors; b) forming silicon dioxide from the precursors, the silicon dioxide being deposited over the substrate at a deposition rate; and c) while depositing, etching the deposited silicon dioxide with the plasma at an, etch rate; a ratio of the deposition rate to the etch rate being at least: about 4:1. In another aspect, the invention includes a method of forming a silicon dioxide layer, including: a) forming a high density plasma proximate a substrate; b) flowing gases into the plasma, at least some of the gases forming silicon dioxide; c) depositing the silicon dioxide formed from the gases over the substrate; and d) while depositing the silicon dioxide, maintaining a temperature of the substrate at greater than or equal to about 500° C.

Abstract: In one aspect, the invention includes a semiconductor processing method comprising exposing silicon, nitrogen and oxygen in gaseous form to a high density plasma during deposition of a silicon, nitrogen and oxygen containing solid layer over a substrate. In another aspect, the invention includes a gate stack forming method, comprising: a) forming a polysilicon layer over a substrate; b) forming a metal silicide layer over the polysilicon layer; c) depositing an antireflective material layer over the metal silicide utilizing a high density plasma; d) forming a layer of photoresist over the antireflective material layer; e) photolithographically patterning the layer of photoresist to form a patterned masking layer from the layer of photoresist; and f) transferring a pattern from the patterned masking layer to the antireflective material layer, metal silicide layer and polysilicon layer to pattern the antireflective material layer, metal silicide layer and polysilicon layer into a gate stack.

Abstract: In one implementation, an etching process includes forming a carbon containing material over a substrate and plasma etching at a temperature of at least 400° C. using a hydrogen or oxygen containing plasma. In one implementation, a plasma etching process includes forming openings in a masking layer over a substrate and etching material beneath the masking through the openings. The masking layer is removed and the substrate is plasma etched at a temperature of at least 400° C. In one implementation, an etching process includes forming a residue over the substrate during a first etching and subsequently plasma etching to remove the residue. In one implementation, a chemical vapor deposition process includes positioning a semiconductor substrate within a plasma enhanced chemical vapor deposition reactor, plasma etching using a first gas chemistry, depositing a material over the substrate within the reactor using a second gas chemistry.

Abstract: Systems and methods are provided for detecting flow in a mass flow controller (MFC). The position of a gate in the MFC is sensed or otherwise determined to monitor flow through the MFC and to immediately or nearly immediately detect a flow failure. In one embodiment of the present invention, a novel MFC is provided. The MFC includes an orifice, a mass flow control gate, an actuator and a gate position sensor. The actuator moves the control gate to control flow through the orifice. The gate position sensor determines the gate position and/or gate movement to monitor flow and immediately or nearly immediately detect a flow failure. According to one embodiment of the present invention, the gate position sensor includes a transmitter for transmitting a signal and a receiver for receiving the signal such that the receiver provides an indication of the position of the gate based on the signal received.

Abstract: The present invention discloses an apparatus having a platen; a polishing pad disposed over the platen; a slurry dispenser disposed over the polishing pad; a cathode connected electrically to the polishing pad; a wafer carrier disposed over the polishing pad;

Abstract: Methods of forming an electrically conductive line include providing a stress inducing material within or a compressive stress inducing layer, operatively adjacent a crystalline material of a first crystalline phase. In addition, such methods include annealing the crystalline material of the first crystalline phase under conditions effective to transform it to a second crystalline phase. Some methods also include providing stress inducing materials into a refractory metal layer. Example compressive stress inducing layers include SiO2 and Si3N4, while example stress inducing materials include Ge, W and Co. Where the compressive stress inducing material is provided on the same side of a wafer over which the crystalline phase material is provided, it is provided to have a thermal coefficient of expansion which is less than the first phase crystalline material. Example and preferred crystalline phase materials having two phases are refractory metal silicides, such as TiSix.

Abstract: The present invention discloses an apparatus having a platen; a polishing pad disposed over the platen; a slurry dispenser disposed over the polishing pad; a cathode connected electrically to the polishing pad; a wafer carrier disposed over the polishing pad; an anode connected electrically to the wafer carrier; and a power supply connected to the anode and the cathode. The present invention further discloses a method to remove a surface layer from a wafer using a polishing pad, a slurry, and an electrical current.

Abstract: Plasma enhanced chemical vapor deposition (PECVD) reactors and methods of effecting the same are described. In accordance with a preferred implementation, a reaction chamber includes first and second electrodes operably associated therewith. A single RF power generator is connected to an RF power splitter which splits the RF power and applies the split power to both the first and second electrodes. Preferably, power which is applied to both electrodes is in accordance with a power ratio as between electrodes which is other than a 1:1 ratio. In accordance with one preferred aspect, the reaction chamber comprises part of a parallel plate PECVD system. In accordance with another preferred aspect, the reaction chamber comprises part of an inductive coil PECVD system. The power ratio is preferably adjustable and can be varied. One manner of effecting a power ratio adjustment is to vary respective electrode surface areas.

Abstract: A semiconductor wafer scrubber has a brush with a nubless outer surface for cleaning the surfaces of a semiconductor wafer. The nubless brush has a body and rotates around a central axis as it contacts the wafer surface. The brush has a central section with an outer diameter less than the diameter of the end sections.

Abstract: Conductive contacts in a semiconductor structure, and methods for forming the conductive components are provided. The contacts are useful for providing electrical connection to active components beneath an insulation layer in integrated circuits such as memory devices. The conductive contacts comprise boron-doped TiCl4-based titanium nitride, and possess a sufficient level adhesion to the insulative layer to eliminate peeling from the sidewalls of the contact opening and cracking of the insulative layer when formed to a thickness of greater than about 200 angstroms.

Abstract: This invention is a process for manufacturing a random access memory array. Each memory cell within the array which results from the process incorporates a stacked capacitor, a silicon nitride-coated access transistor gate electrode, and a self-aligned high-aspect-ratio digit line contact having a tungsten plug which extends from the substrate to a metal interconnect structure located at a level above the stacked capacitor. The contact opening is lined with titanium metal that is in contact with the substrate and with titanium nitride that is in contact with the plug. Both the titanium metal and the titanium nitride are deposited via chemical vapor deposition reactions.

Abstract: A new process for depositing titanium metal layers via chemical vapor deposition is disclosed. The process provides deposited titanium layers having a high degree of conformality, even in trenches and contact openings having aspect ratios greater than 1:5. The reaction gases for the improved process are titanium tetrachloride and a hydrocarbon gas, which for a preferred embodiment of the process is methane. The reaction is carried out in a plasma environment created by a radio frequency source greater than 10 KHz. The key to obtaining titanium metal as a reaction product, rather than titanium carbide, is to set the plasma-sustaining electrical power within a range that will remove just one hydrogen atom from each molecule of the hydrocarbon gas. In a preferred embodiment of the process, highly reactive methyl radicals (CH3-) are formed from methane gas. These radicals attack the titanium-chlorine bonds of the tetrachloride molecule and form chloromethane, which is evacuated from the chamber as it is formed.

Abstract: A chemical vapor deposition apparatus includes a deposition chamber defined at least in part by at least one of a chamber sidewall and a chamber base wall. A substrate holder is received within the chamber. At least one process chemical inlet to the deposition chamber is included. At least one of the chamber sidewall and chamber base wall includes a chamber surface having a plurality of purge gas inlets to the chamber therein. The purge gas inlets are separate from the at least one process chemical inlet. A purge gas inlet passageway is provided in fluid communication with the purge gas inlets. Further implementations, including deposition method implementations, are contemplated.