Abstract: A method including forming a chemically soluble coating on a plurality exposed contacts on a surface of a circuit substrate; scribing the surface of the substrate along scribe areas; and after scribing, removing a portion of the coating. A method including forming a circuit structure comprises a plurality of exposed contacts on a surface, a location of the exposed contacts defined by a plurality of scribe streets; forming a coating comprising a chemically soluble material on the exposed contacts; scribing the surface of the substrate along the scribe streets; and after scribing, removing the coating. A method including coating a surface of a circuit substrate comprising a plurality of exposed contacts with a chemically soluble material; scribing the surface of the substrate along scribe areas; removing the coating; and sawing the substrate in the scribe areas.

Abstract: Systems and methods are provided for detecting flow in a mass flow controller (MFC). The position of a gate in the MFC is sensed or otherwise determined to monitor flow through the MFC and to immediately or nearly immediately detect a flow failure. In one embodiment of the present invention, a novel MFC is provided. The MFC includes an orifice, a mass flow control gate, an actuator and a gate position sensor. The actuator moves the control gate to control flow through the orifice. The gate position sensor determines the gate position and/or gate movement to monitor flow and immediately or nearly immediately detect a flow failure. According to one embodiment of the present invention, the gate position sensor includes a transmitter for transmitting a signal and a receiver for receiving the signal such that the receiver provides an indication of the position of the gate based on the signal received.

Abstract: Methods of chemical vapor deposition include providing a deposition chamber defined at least in part by at least one of a chamber sidewall and a chamber base wall. At least one process chemical inlet to the deposition chamber is included. A substrate is positioned within the chamber and a process gas is provided over the substrate effective to deposit material onto the substrate. While providing the process gas, a purge gas is emitted into the chamber from a plurality of purge gas inlets comprised by at least one chamber wall surface. The purge gas inlets are separate from the at least one process chemical inlet and the emitting forms an inert gas curtain over the chamber wall surface.

Abstract: A method of forming a silicon dioxide layer includes forming a high density plasma proximate a substrate, the plasma comprising silicon dioxide precursors; forming silicon dioxide from the precursors, the silicon dioxide being deposited over the substrate at a deposition rate; and while depositing, etching the deposited silicon dioxide with the plasma at an etch rate; a ratio of the deposition rate to the etch rate being at least about 4:1. Another method includes forming a high density plasma proximate a substrate; flowing gases into the plasma, at least some of the gases forming silicon dioxide; depositing the silicon dioxide formed from the gases over the substrate; and while depositing the silicon dioxide, maintaining a temperature of the substrate at greater than or equal to about 500° C. As an alternative, the method may include not cooling the substrate with a coolant gas while depositing the silicon dioxide.

Abstract: A process for PECVD of selected material films on a substrate comprising the steps of placing a substrate in a PECVD chamber and maintaining the chamber under vacuum pressure while introducing a precursor gas, a reactant gas, and an ionization enhancer agent into the chamber. A plasma is generated from the gases within the chamber. The energy generating the plasma causes the formation of charged species. The resulting charged species of the ionization enhancer agent assists in the formation of chemically reactive species of at least the precursor.

Abstract: A semiconductor wafer scrubber has a brush with a nubless outer surface for cleaning the surfaces of a semiconductor wafer. The nubless brush has a body and rotates around a central axis as it contacts the wafer surface. The brush has a central section with an outer diameter less than the diameter of the end sections.

Abstract: In one aspect, the invention includes a semiconductor processing method comprising exposing silicon, nitrogen and oxygen in gaseous form to a high density plasma during deposition of a silicon, nitrogen and oxygen containing solid layer over a substrate. In another aspect, the invention includes a gate stack forming method, comprising: a) forming a polysilicon layer over a substrate; b) forming a metal silicide layer over the polysilicon layer; c) depositing an antireflective material layer over the metal silicide utilizing a high density plasma; d) forming a layer of photoresist over the antireflective material layer; e) photolithographically patterning the layer of photoresist to form a patterned masking layer from the layer of photoresist; and f) transferring a pattern from the patterned masking layer to the antireflective material layer, metal silicide layer and is polysilicon layer to pattern the antireflective material layer, metal silicide layer and polysilicon layer into a gate stack.

Abstract: A method of forming a crystalline phase material includes, a) providing a stress inducing material within or operatively adjacent a crystalline material of a first crystalline phase; and b) annealing the crystalline material of the first crystalline phase under conditions effective to transform it to a second crystalline phase. The stress inducing material preferably induces compressive stress within the first crystalline phase during the anneal to the second crystalline phase to lower the required activation energy to produce a more dense second crystalline phase. Example compressive stress inducing layers include SiO2 and Si3N4, while example stress inducing materials for providing into layers are Ge, W and Co. Where the compressive stress inducing material is provided on the same side of a wafer over which the crystalline phase material is provided, it is provided to have a thermal coefficient of expansion which is less than the first phase crystalline material.

Abstract: Systems and methods are provided for detecting flow in a mass flow controller (MFC). The position of a gate in the MFC is sensed or otherwise determined to monitor flow through the MFC and to immediately or nearly immediately detect a flow failure. In one embodiment of the present invention, a novel MFC is provided. The MFC includes an orifice, a mass flow control gate, an actuator and a gate position sensor. The actuator moves the control gate to control flow through the orifice. The gate position sensor determines the gate position and/or gate movement to monitor flow and immediately or nearly immediately detect a flow failure. According to one embodiment of the present invention, the gate position sensor includes a transmitter for transmitting a signal and a receiver for receiving the signal such that the receiver provides an indication of the position of the gate based on the signal received.

Abstract: Systems and methods are provided for detecting flow in a mass flow controller (MFC). The position of a gate in the MFC is sensed or otherwise determined to monitor flow through the MFC and to immediately or nearly immediately detect a flow failure. In one embodiment of the present invention, a novel MFC is provided. The MFC includes an orifice, a mass flow control gate, an actuator and a gate position sensor. The actuator moves the control gate to control flow through the orifice. The gate position sensor determines the gate position and/or gate movement to monitor flow and immediately or nearly immediately detect a flow failure. According to one embodiment of the present invention, the gate position sensor includes a transmitter for transmitting a signal and a receiver for receiving the signal such that the receiver provides an indication of the position of the gate based on the signal received.

Abstract: Systems and methods are provided for detecting flow in a mass flow controller (MFC). The position of a gate in the MFC is sensed or otherwise determined to monitor flow through the MFC and to immediately or nearly immediately detect a flow failure. In one embodiment of the present invention, a novel MFC is provided. The MFC includes an orifice, a mass flow control gate, an actuator and a gate position sensor. The actuator moves the control gate to control flow through the orifice. The gate position sensor determines the gate position and/or gate movement to monitor flow and immediately or nearly immediately detect a flow failure. According to one embodiment of the present invention, the gate position sensor includes a transmitter for transmitting a signal and a receiver for receiving the signal such that the receiver provides an indication of the position of the gate based on the signal received.

Abstract: Systems and methods are provided for detecting flow in a mass flow controller (MFC). The position of a gate in the MFC is sensed or otherwise determined to monitor flow through the MFC and to immediately or nearly immediately detect a flow failure. In one embodiment of the present invention, a novel MFC is provided. The MFC includes an orifice, a mass flow control gate, an actuator and a gate position sensor. The actuator moves the control gate to control flow through the orifice. The gate position sensor determines the gate position and/or gate movement to monitor flow and immediately or nearly immediately detect a flow failure. According to one embodiment of the present invention, the gate position sensor includes a transmitter for transmitting a signal and a receiver for receiving the signal such that the receiver provides an indication of the position of the gate based on the signal received.

Abstract: Systems and methods are provided for detecting flow in a mass flow controller (MFC). The position of a gate in the MFC is sensed or otherwise determined to monitor flow through the MFC and to immediately or nearly immediately detect a flow failure. In one embodiment of the present invention, a novel MFC is provided. The MFC includes an orifice, a mass flow control gate, an actuator and a gate position sensor. The actuator moves the control gate to control flow through the orifice. The gate position sensor determines the gate position and/or gate movement to monitor flow and immediately or nearly immediately detect a flow failure. According to one embodiment of the present invention, the gate position sensor includes a transmitter for transmitting a signal and a receiver for receiving the signal such that the receiver provides an indication of the position of the gate based on the signal received.

Abstract: In one embodiment, the invention provides a method comprising fabricating a die bump on a die, the die bump being shaped and dimensioned to at least reduce the flow of solder material used, to attach the die bump to a package substrate, towards an under bump metallurgy (UBM) layer located below the die bump. Advantageously, the method may comprise performing a substrate reflow operation to attach the package substrate to the die bump, without performing a separate wafer reflow operation to reflow the die bump.

Abstract: A method of forming a silicon dioxide layer includes forming a high density plasma proximate a substrate, the plasma comprising silicon dioxide precursors; forming silicon dioxide from the precursors, the silicon dioxide being deposited over the substrate at a deposition rate; and while depositing, etching the deposited silicon dioxide with the plasma at an etch rate; a ratio of the deposition rate to the etch rate being at least about 4:1. Another method includes forming a high density plasma proximate a substrate; flowing gases into the plasma, at least some of the gases forming silicon dioxide; depositing the silicon dioxide formed from the gases over the substrate; and while depositing the silicon dioxide, maintaining a temperature of the substrate at greater than or equal to about 500° C. As an alternative, the method may include not cooling the substrate with a coolant gas while depositing the silicon dioxide.

Abstract: A high aspect ratio contact structure using a metal silicide adhesion layer that is interposed between titanium and titanium nitride (TiN) to promote adhesion of TiN to Ti. The metal silicide adhesion layer created from silicon doped CVD Ti can be deposited over the unreacted Ti after the silicidation reaction or deposited directly on the silicon substrate in place of CVD Ti. The contact structure further includes contact fill that is comprised of TiCl4 based TiN, which affords improved step coverage in the contact structure.

Abstract: A process for PECVD of selected material films on a substrate comprising the steps of placing a substrate in a PECVD chamber and maintaining the chamber under vacuum pressure while introducing a precursor gas, a reactant gas, and an ionization enhancer agent into the chamber. A plasma is generated from the gases within the chamber. The energy generating the plasma causes the formation of charged species. The resulting charged species of the ionization enhancer agent assists in the formation of chemically reactive species of at least the precursor.

Abstract: A process for PECVD of selected material films on a substrate comprising the steps of placing a substrate in a PECVD chamber and maintaining the chamber under vacuum pressure while introducing a precursor gas, a reactant gas, and an ionization enhancer agent into the chamber. A plasma is generated from the gases within the chamber. The energy generating the plasma causes the formation of charged species. The resulting charged species of the ionization enhancer agent assists in the formation of chemically reactive species of at least the precursor.

Abstract: A method of forming a crystalline phase material includes, a) providing a stress inducing material within or operatively adjacent a crystalline material of a first crystalline phase; and b) annealing the crystalline material of the first crystalline phase under conditions effective to transform it to a second crystalline phase. The stress inducing material preferably induces compressive stress within the first crystalline phase during the anneal to the second crystalline phase to lower the required activation energy to produce a more dense second crystalline phase. Example compressive stress inducing layers include SiO2 and Si3N4, while example stress inducing materials for providing into layers are Ge, W and Co. Where the compressive stress inducing material is provided on the same side of a wafer over which the crystalline phase material is provided, it is provided to have a thermal coefficient of expansion which is less than the first phase crystalline material.

Abstract: Contact areas comprising doped semiconductor material at the bottom of contact holes are cleaned in a hot hydrogen plasma and exposed in situ during and/or separately from the hot hydrogen clean to a plasma containing the same dopant species as in the semiconductor material so as to partially, completely, or more than completely offset any loss of dopant due to the hot hydrogen clean. A protective conductive layer such as a metal silicide is then formed over the contact area in situ. The resulting integrated circuit has contacts with interfaces such as a silicide interfaces to contact areas having a particularly favorable dopant profile and concentration adjacent the silicide interfaces.