Abstract: A structure and method operable to create a reusable template for detachable thin semiconductor substrates is provided. The template has a shape such that the 3-D shape is substantially retained after each substrate release. Prior art reusable templates may have a tendency to change shape after each subsequent reuse; the present disclosure aims to address this and other deficiencies from the prior art, therefore increasing the reuse life of the template.

Abstract: A structure and method operable to create a reusable template for detachable thin semiconductor substrates is provided. The template has a shape such that the 3-D shape is substantially retained after each substrate release. Prior art reusable templates may have a tendency to change shape after each subsequent reuse; the present disclosure aims to address this and other deficiencies from the prior art, therefore increasing the reuse life of the template.

Abstract: Techniques for controlling an output property during wafer processing include forwarding feedforward and feedback information between functional units in a wafer manufacturing facility. At least some embodiments of the invention envision implementing such techniques in a copper wiring module to optimize a sheet resistance or an interconnect line resistance. Initially, a first wafer property is measured during or after processing by a plating process. Subsequently, the wafer is forwarded to a polishing process. A second wafer property is then measured during or after processing by the second process. At least one of these first and second wafer properties are used to optimize the second process. Specifically, one or more target parameters of a second process recipe are adjusted in a manner that obtains a desired final output property on the wafer by using these first and second wafer properties.

Abstract: A structure and method operable to create a reusable template for detachable thin semiconductor substrates is provided. The template has a shape such that the 3-D shape is substantially retained after each substrate release. Prior art reusable templates may have a tendency to change shape after each subsequent reuse; the present disclosure aims to address this and other deficiencies from the prior art, therefore increasing the reuse life of the template.

Abstract: Methods for manufacturing three-dimensional thin-film solar cells using a template. The template comprises a template substrate comprising a plurality of three-dimensional surface features. The three-dimensional thin-film solar cell substrate is formed by forming a sacrificial layer on the template, subsequently depositing a semiconductor layer, selectively etching the sacrificial layer, and releasing the semiconductor layer from the template. Select portions of the three-dimensional thin-film solar cell substrate are then doped with a first dopant, while other select portions are doped with a second dopant. Next, selective emitter and base metallization regions are formed using a PECVD shadow mask process.

Abstract: A method operable to produce integrated 3-dimension and planar metallization structure for thin film solar cells is provided. This method involves depositing a thin film on a template mask, the template mask having both substantially flat and textured areas. The thin film is then released from the template mask. Emitters are formed on the thin film. Finally, metallization of the substantially flat areas takes place.

Abstract: The present disclosure presents a three-dimensional thin film solar cell (3-D TFSC) substrate having enhanced mechanical strength, light trapping, and metal modulation coverage properties. The substrate includes a plurality of unit cells, which may or may not be different. Unit cells are defined as a small self-contained geometrical pattern which may be repeated. Each unit cell structure includes a wall enclosing a trench. Further, the unit cell includes an aperture having an aperture diameter. For the purposes of the present disclosure, the dimensions of interest include wall thickness, wall height, and aperture diameter. A pre-determined variation in these dimensions among unit cells across the substrate produces specific advantages.

Abstract: The etch depth during trench over via etch of a dual damascene structure in a dielectric film stack is controlled to be the same over the dense area and the open area of a substrate and solve micro-loading problems. The trench etch process is adapted to include a forward micro-loading etching process and a reverse micro-loading etching process using two etch chemistries together with the inclusion of a dopant material layer or an organic fill material layer during the deposition of the dielectric film stack. In one embodiment, etching of trenches over vias is switched from forward micro-loading to reverse micro-loading once etching of the dielectric film stack is reached at a predetermined location of a dopant material layer. In another embodiment, etching of an organic trench filling material layer is performed in a reverse micro-loading process followed by etching the dielectric film stack in a forward micro-loading process.

Abstract: Devices and/or methods that facilitate reducing cross-talk noise and/or complementary bit disturb between adjacent storage elements in a memory device are presented. A memory device includes a memory array with wordlines formed in a zig-zag pattern such that each wordline can have segments that are parallel to the x-axis and other segments that are angled from a direction parallel to the x-axis based in part on a predetermined angle. Adjacent storage elements can be positioned at respective ends of an angled segment of a wordline to facilitate increasing the distance between such storage elements, as compared to the distance between storage elements associated with an orthogonal memory array, where the increase in distance can be based in part on the predetermined angle. The size of the memory array can be the same or substantially the same size, as compared to an orthogonal memory array.

Abstract: The present invention provides integrated circuit fabrication methods and devices wherein shunted interconnect lines are formed. The shunted interconnect lines are formed in a dielectric stack comprising (1) a first dielectric layer having dense interconnect lines that form a first dielectric layer dense line subset and (2) a sequentially deposited (i) etch stop layer, (ii) second dielectric layer and (iii) third dielectric layer. An interconnect line trench design is prepared in the third dielectric layer. An interconnect line trench is formed in the third dielectric layer according to the interconnect line trench design. One or more electrically conductive shunts are fabricated in the second dielectric layer such that the one or more shunts (1) extend from the interconnect line trench to the etch stop layer and (2) do not cross over the first dielectric layer dense line subset.

Abstract: The present invention provides integrated circuit fabrication methods and devices wherein shunted interconnect lines are formed. The shunted interconnect lines are formed in a dielectric stack comprising (1) a first dielectric layer having dense interconnect lines that form a first dielectric layer dense line subset and (2) a sequentially deposited (i) etch stop layer, (ii) second dielectric layer and (iii) third dielectric layer. An interconnect line trench design is prepared in the third dielectric layer. An interconnect line trench is formed in the third dielectric layer according to the interconnect line trench design. One or more electrically conductive shunts are fabricated in the second dielectric layer such that the one or more shunts (1) extend from the interconnect line trench to the etch stop layer and (2) do not cross over the first dielectric layer dense line subset.

Abstract: The etch depth during trench over via etch of a dual damascene structure in a dielectric film stack is controlled to be the same over the dense area and the open area of a substrate and solve micro-loading problems. The trench etch process is adapted to include a forward micro-loading etching process and a reverse micro-loading etching process using two etch chemistries together with the inclusion of a dopant material layer or an organic fill material layer during the deposition of the dielectric film stack. In one embodiment, etching of trenches over vias is switched from forward micro-loading to reverse micro-loading once etching of the dielectric film stack is reached at a predetermined location of a dopant material layer. In another embodiment, etching of an organic trench filling material layer is performed in a reverse micro-loading process followed by etching the dielectric film stack in a forward micro-loading process.

Abstract: A method for forming a damascene structure utilizes dual hard mask layers and a thin etch stop layer, and does not require a sacrificial layer within the via. A floating etch stop layer can additionally be used. The dual hard masks may be formed of dielectric and neither of the hard masks is required to contain metal. The thin etch stop layer reduces capacitance problems.

Abstract: Techniques for controlling an output property during wafer processing include forwarding feedforward and feedback information between functional units in a wafer manufacturing facility. At least some embodiments of the invention envision implementing such techniques in a copper wiring module to optimize a sheet resistance or an interconnect line resistance. Initially, a first wafer property is measured during or after processing by a plating process. Subsequently, the wafer is forwarded to a polishing process. A second wafer property is then measured during or after processing by the second process. At least one of these first and second wafer properties are used to optimize the second process. Specifically, one or more target parameters of a second process recipe are adjusted in a manner that obtains a desired final output property on the wafer by using these first and second wafer properties.

Abstract: A method and system of processing a semiconductor substrate includes, in one or more embodiments, depositing a protective layer on the substrate surface comprising a conductive element disposed in a dielectric material; processing the protective layer to expose the conductive element; electrolessly depositing a metallic passivating layer onto the conductive element; and removing at least a portion of the protective layer from the substrate after electroless deposition. In another aspect, a method and system of processing a semiconductor includes depositing a metallic passivating layer onto a substrate surface comprising a conductive element, masking the passivating layer to protect the underlying conductive element of the substrate surface, removing the unmasked passivating layer, and removing the mask from the passivating layer.

Abstract: An apparatus for performing intra-tool monitoring and control within a multi-step processing system. The apparatus provides a metrology station located between each of a plurality of semiconductor wafer processing tools such that measurements can be made on wafers as they are passed from one tool to another providing intra tool monitoring. The data collected by the metrology station is coupled to a metrology data analyzer, which determines whether any of the plurality of wafer processing tools should be adjusted to improve the processing of the overall wafer. As such, the output of the metrology data analyzer provides control parameters to process controllers connected controllers connected to each of the tools within the semiconductor wafer processing system. Consequently, the operation of the metrology stations and the metrology data analyzer provides both feed forward and feed back data to control the tools based upon certain information that is gathered within the metrology station.

Abstract: A method and apparatus for performing intra-tool monitoring and control within a multi-step processing system. The method monitors the processing of a workpiece as the workpiece is processed by independently operating processing tools and produces control parameters for the various independently operating processing tools to optimize the processing of the workpiece. More specifically, the apparatus provides a metrology station located between each of a plurality of semiconductor wafer processing tools such that measurements can be made on wafers as they are passed from one tool to another providing intra tool monitoring. The data collected by the metrology station is coupled to a metrology data analyzer, which determines whether any of the plurality of wafer processing tools should be adjusted to improve the processing of the overall wafer.

Abstract: The present invention provides integrated circuit fabrication methods and devices wherein triple damascene structures are formed in five consecutive dielectric layers (312, 314, 316, 318 and 320), using two etching sequences. A first etching sequence comprising: depositing a first etch mask layer (322), on the fifth (top) layer (320), developing a power line trench pattern (324) and a via pattern (326) in the first mask layer, simultaneously etching the power line trench pattern (324) and the via pattern (326) through the top three dielectric layers (316, 318, 320), and removing the first etch mask layer.

Abstract: A method and apparatus for performing intra-tool monitoring and control within a multi-step processing system. The method monitors the processing of a workpiece as the workpiece is processed by independently operating processing tools and produces control parameters for the various independently operating processing tools to optimize the processing of the workpiece. More specifically, the apparatus provides a metrology station located between each of a plurality of semiconductor wafer processing tools such that measurements can be made on wafers as they are passed from one tool to another providing intra tool monitoring. The data collected by the metrology station is coupled to a metrology data analyzer, which determines whether any of the plurality of wafer processing tools should be adjusted to improve the processing of the overall wafer.

Abstract: A method and system of processing a semiconductor substrate includes, in one or more embodiments, depositing a protective layer on the substrate surface comprising a conductive element disposed in a dielectric material; processing the protective layer to expose the conductive element; electrolessly depositing a metallic passivating layer onto the conductive element; and removing at least a portion of the protective layer from the substrate after electroless deposition. In another aspect, a method and system of processing a semiconductor includes depositing a metallic passivating layer onto a substrate surface comprising a conductive element, masking the passivating layer to protect the underlying conductive element of the substrate surface, removing the unmasked passivating layer, and removing the mask from the passivating layer.