Abstract: A method and apparatus for performing intra-tool monitoring and control within a multi-step processing system. The method monitors the processing of a workpiece as the workpiece is processed by independently operating processing tools and produces control parameters for the various independently operating processing tools to optimize the processing of the workpiece. More specifically, the apparatus provides a metrology station located between each of a plurality of semiconductor wafer processing tools such that measurements can be made on wafers as they are passed from one tool to another providing intra tool monitoring. The data collected by the metrology station is coupled to a metrology data analyzer, which determines whether any of the plurality of wafer processing tools should be adjusted to improve the processing of the overall wafer.

Abstract: A method for forming a microelectronics device is disclosed. In one embodiment, the method includes depositing a conductive structure on a substrate. A first layer comprising silicon and nitrogen is formed on the substrate. A second layer comprising silicon and nitrogen is then formed on the first layer. The nitrogen to silicon ratio in the first layer is greater than the nitrogen to silicon ratio in the second layer.

Abstract: A method for forming a microelectronics device is disclosed. In one embodiment, the method includes depositing a conductive structure on a substrate. A first layer comprising silicon and nitrogen is formed on the substrate. A second layer comprising silicon and nitrogen is then formed on the first layer. The nitrogen to silicon ratio in the first layer is greater than the nitrogen to silicon ratio in the second layer.

Abstract: Techniques for controlling an output property during wafer processing include forwarding feedforward and feedback information between functional units in a wafer manufacturing facility. At least some embodiments of the invention envision implementing such techniques in a copper wiring module to optimize a sheet resistance or an interconnect line resistance. Initially, a first wafer property is measured during or after processing by a plating process. Subsequently, the wafer is forwarded to a polishing process. A second wafer property is then measured during or after processing by the second process. At least one of these first and second wafer properties are used to optimize the second process. Specifically, one or more target parameters of a second process recipe are adjusted in a manner that obtains a desired final output property on the wafer by using these first and second wafer properties.

Abstract: A method for forming a conductive feature on a substrate having a connection between the metal deposited in an interconnect opening and an underlying metal feature is presented. The underlying metal feature is etched and a barrier layer is deposited on the structure such that the metal deposited in the interconnect opening and the metal deposited in the metal feature are not isolated from each other by an intervening structure or layer.

Abstract: In one aspect of the invention, a method for forming interconnects on a substrate is provided. A metal passivation layer is selectively formed on conductive elements of the substrate. Thereafter, one or more dielectric layers are deposited over the metal passivation layer. Interconnect lines and vias are then patterned and etched into the one or more dielectric layers. A conductive layer is subsequently deposited over the interconnect lines and vias. In another aspect of the invention, the selective deposition process may comprise electroless deposition of the metal passivation layer. Alternatively, the selective deposition process may comprise a selective chemical vapor deposition process. The metal passivation layer may also be formed by depositing a metal alloy of copper over the conductive element, depositing a copper layer over the metal alloy, and annealing the metal alloy. In another aspect still, a metal passivation layer is selectively deposited over the conductive element of the substrate.

Abstract: The present invention provides integrated circuit fabrication methods and devices wherein dual damascene structures are formed which compensate for misalignment between the via pattern and the trench pattern by widening the trench at the point where the misalignment has occurred. Methods and devices are also provided wherein the trench width is not affected by misalignment thus preventing electrical shorts between closely spaced interconnect lines, this technique results in a reduction of the width of the via. These dual damascene structures utilize two dielectric layers (210 and 216) having similar etching characteristics. Additionally, a hard mask layer (218) and an etch stop layer (214) having similar etching characteristics are used in these structures. In additional embodiments, manufacturing systems (610) are provided for fabricating IC structures. These systems include a controller (600) for interacting with a plurality of fabrication stations (620, 622, 624, 626, 628, 630 and 632).

Abstract: The present invention provides integrated circuit fabrication methods and devices wherein dual damascene structures (552 and 558) are formed in a dielectric stack including three dielectric layers (516, 518 and 530). Via patterns (522 and 524) for these structures have a rectangular shape and are wider than the corresponding overlaying trench patterns (534 and 536). Another embodiment of the present invention provides dual damascene structures (860 and 862) employing a sacrificial etch segment (828) in an etch stop layer (818) of a dielectric stack (810, 816 and 842). The sacrificial etch segment is positioned between adjacent dual damascene interconnect lines (864 and 866) which are formed on the etch stop layer (818). In additional embodiments, manufacturing systems (1210) are provided for fabricating IC structures. These systems include a controller (1200) which is adapted for interacting with a plurality of fabrication stations (1220, 1222, 1224, 1226, 1228 and 1230).

Abstract: A method is provided that includes (1) receiving information about a substrate processed within a barrier/seed layer deposition subsystem from an integrated inspection system of the subsystem; (2) determining an electroplating process to perform within an electroplating subsystem based at least in part on the information received from the inspection system of the barrier/seed layer deposition subsystem; (3) directing the electroplating subsystem to deposit a fill layer on the substrate based on the electroplating process; (4) receiving information about the fill layer from an integrated inspection system of the electroplating subsystem; (5) determining a planarization process to perform within a planarization subsystem based at least in part on the information received from the inspection system of the electroplating subsystem; and (6) directing the planarization subsystem to planarize the substrate based on the planarization process.

Abstract: A method and apparatus for performing intra-tool monitoring and control within a multi-step processing system. The method monitors the processing of a workpiece as the workpiece is processed by independently operating processing tools and produces control parameters for the various independently operating processing tools to optimize the processing of the workpiece. More specifically, the apparatus provides a metrology station located between each of a plurality of semiconductor wafer processing tools such that measurements can be made on wafers as they are passed from one tool to another providing intra tool monitoring. The data collected by the metrology station is coupled to a metrology data analyzer, which determines whether any of the plurality of wafer processing tools should be adjusted to improve the processing of the overall wafer.

Abstract: The present invention provides integrated circuit fabrication methods and devices wherein dual damascene structures (332 and 334) are formed in consecutive dielectric layers (314 and 316) having dissimilar etching characteristics. The present invention also provides for such methods and devices wherein these dielectric layers have different dielectric constants. Additional embodiments of the present invention include the use of single layer masks, such as silicon-based photosensitive materials which form a hard mask (622) upon exposure to radiation. In additional embodiments, manufacturing systems (710) are provided for fabricating IC structures. These systems include a controller (700) which is adapted for interacting with a plurality of fabrication stations (720, 722, 724, 726, 728 and 730).

Abstract: The present invention provides Cu lines which are enclosed within Cu diffusion barrier layers, for IC structures such as semiconductor devices. The Cu lines (310) have conventional top (316) and bottom (318) Cu diffusion barrier layers and novel sidewall layers (324 and 326) comprising Cu diffusion barrier materials. The present invention also provides for conductive interconnect lines for semiconductor devices which compensate partly or completely for a misalignment between the line etch pattern and the underlying contact element, such as a via plug. The misalignment tolerant line (430) is formed by fabricating novel sidewalls (438 and 440) on the line wherein the sidewalls have a thickness which equals or exceeds the width of the gap (431) which is caused by the misalignment. The misalignment tolerant line compensates for the misalignment gap and thereby prevents etching a trench in the contact element.

Abstract: The present invention provides integrated circuit fabrication methods and devices wherein triple damascene structures are formed in five consecutive dielectric layers (312, 314, 316, 318 and 320), using two etching sequences. A first etching sequence comprising: depositing a first etch mask layer (322), on the fifth (top) layer (320), developing a power line trench pattern (324) and a via pattern (326) in the first mask layer, simultaneously etching the power line trench pattern (324) and the via pattern (326) through the top three dielectric layers (316, 318, 320), and removing the first etch mask layer.

Abstract: The present invention provides integrated circuit fabrication methods and devices wherein triple damascene structures are formed in five consecutive dielectric layers (312, 314, 316, 318 and 320), using two etching sequences. A first etching sequence comprising: depositing a first etch mask layer (322), on the fifth (top) layer (320), developing a power line trench pattern (324) and a via pattern (326) in the first mask layer, simultaneously etching the power line trench pattern (324) and the via pattern (326) through the top three dielectric layers (316, 318, 320), and removing the first etch mask layer.

Abstract: The present invention provides integrated circuit fabrication methods and devices wherein triple damascene structures are formed in five consecutive dielectric layers (312, 314, 316, 318 and 320), using two etching sequences. A first etching sequence comprising: depositing a first etch mask layer (322), on the fifth (top) layer (320), developing a power line trench pattern (324) and a via pattern (326) in the first mask layer, simultaneously etching the power line trench pattern (324) and the via pattern (326) through the top three dielectric layers (316, 318, 320), and removing the first etch mask layer.

Abstract: The present invention provides integrated circuit fabrication methods and devices wherein dual damascene structures are formed which compensate for misalignment between the via pattern and the trench pattern by widening the trench at the point where the misalignment has occurred. Methods and devices are also provided wherein the trench width is not affected by misalignment thus preventing electrical shorts between closely spaced interconnect lines, this technique results in a reduction of the width of the via. These dual damascene structures utilize two dielectric layers (210 and 216) having similar etching characteristics. Additionally, a hard mask layer (218) and an etch stop layer (214) having similar etching characteristics are used in these structures such that the etching characteristics of the dielectric layers are dissimilar to the etching characteristics of the hard mask and the etch stop layer. A trench (224) is formed in the hard mask layer (218).