Patents by Inventor Suketu Arun Parikh
Suketu Arun Parikh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230360965Abstract: A method for etching a metal containing feature is provided. Using a pattern mask, layers of material are etched to expose a portion of a metal containing feature. At least a portion of the exposed metal containing feature is etched, and is replaced by the growth of a filler dielectric. The etched portion of the metal containing feature and the filler dielectric reduce the unwanted conductivity between adjacent metal containing features.Type: ApplicationFiled: July 21, 2023Publication date: November 9, 2023Inventor: Suketu Arun PARIKH
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Patent number: 11749561Abstract: A method for etching a metal containing feature is provided. Using a pattern mask, layers of material are etched to expose a portion of a metal containing feature. At least a portion of the exposed metal containing feature is etched, and is replaced by the growth of a filler dielectric. The etched portion of the metal containing feature and the filler dielectric reduce the unwanted conductivity between adjacent metal containing features.Type: GrantFiled: June 10, 2021Date of Patent: September 5, 2023Assignee: Applied Materials, Inc.Inventor: Suketu Arun Parikh
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Patent number: 11682668Abstract: Logic devices and methods of forming logic devices are described. An epitaxial channel is formed orthogonally to a horizontal plane of a substrate surface with a stack or horizontal transistors on the substrate surface. The first horizontal transistor having a first length and a first step, the second horizontal transistor having a second length and a second step and a third horizontal transistor has a third length and a third step. Each of the horizontal transistors is separated from adjacent layers by a horizontal isolation layer.Type: GrantFiled: October 13, 2021Date of Patent: June 20, 2023Assignee: Applied Materials, Inc.Inventors: Suketu Arun Parikh, Sanjay Natarajan
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Patent number: 11658041Abstract: Embodiments provided herein generally relate to methods of modifying portions of layer stacks. The methods include forming deep trenches and narrow trenches, such that a desirably low voltage drop between layers is achieved. A method of forming a deep trench includes etching portions of a flowable dielectric, such that a deep metal contact is disposed below the deep trench. The deep trench is selectively etched to form a modified deep trench. A method of forming a super via includes forming a super via trench through a second layer stack of a layer superstack. The methods disclosed herein allow for decreasing the resistance, and thus the voltage drop, of features in a semiconductor layer stack.Type: GrantFiled: January 25, 2021Date of Patent: May 23, 2023Assignee: Applied Materials, Inc.Inventor: Suketu Arun Parikh
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Publication number: 20230064183Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes front side processing to form a deep source/drain cavity and filling the cavity with a sacrificial material. The sacrificial material is then removed during processing of the backside to form a backside power rail via that is filled with a metal fill.Type: ApplicationFiled: August 29, 2022Publication date: March 2, 2023Applicant: Applied Materials, Inc.Inventors: Suketu Arun Parikh, Ashish Pal, El Mehdi Bazizi, Andrew Yeoh, Nitin K. Ingle, Arvind Sundarrajan, Guan Huei See, Martinus Maria Berkens, Sameer A. Deshpande, Balasubramanian Pranatharthiharan, Yen-Chu Yang
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Publication number: 20230061392Abstract: Semiconductor devices and methods of manufacturing the same are described. A silicon wafer is provided and a buried etch stop layer is formed on the silicon wafer. The wafer is then subjected to device and front-end processing. After front-end processing, the wafer undergoes hybrid bonding, and then the wafer is thinned. To thin the wafer, the silicon substrate layer, which has a starting first thickness, is ground to a second thickness, the second thickness less than the first thickness. After grinding, the silicon wafer is subjected to chemical mechanical planarization (CMP), followed by etching and CMP buffing, to reduce the thickness of the silicon to a third thickness, the third thickness less than the second thickness.Type: ApplicationFiled: August 29, 2022Publication date: March 2, 2023Applicant: Applied Materials, Inc.Inventors: Suketu Arun Parikh, Ashish Pal, El Mehdi Bazizi, Andrew Yeoh, Nitin K. Ingle, Arvind Sundarrajan, Guan Huei See, Martinus Maria Berkens, Sameer A. Deshpande, Balasubramanian Pranatharthiharan, Yen-Chu Yang
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Publication number: 20230068312Abstract: Semiconductor devices and methods of manufacturing the same are described. Transistors are fabricated using a standard process flow. A via opening extending from the top surface of the substrate to a bottom surface of the wafer device is formed, thus allowing nano TSV for high density packaging, as well as connecting the device to the backside power rail. A metal is deposited in the via opening, and the bottom surface of the wafer device is bound to a bonding wafer. The substrate is optionally thinned, and a contact electrically connected to the metal is formed.Type: ApplicationFiled: August 29, 2022Publication date: March 2, 2023Applicant: Applied Materials, Inc.Inventors: Suketu Arun Parikh, Ashish Pal, El Mehdi Bazizi, Andrew Yeoh, Nitin K. Ingle, Arvind Sundarrajan, Guan Huei See, Martinus Maria Berkens, Sameer A. Deshpande, Balasubramanian Pranatharthiharan, Yen-Chu Yang
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Patent number: 11557509Abstract: A method for etching a metal containing feature is provided. Using a pattern mask, layers of material are etched to expose a portion of a metal containing feature. At least a portion of the exposed metal containing feature is etched, and is replaced by the growth of a filler dielectric. The etched portion of the metal containing feature and the filler dielectric reduce the unwanted conductivity between adjacent metal containing features.Type: GrantFiled: November 21, 2019Date of Patent: January 17, 2023Assignee: Applied Materials, Inc.Inventor: Suketu Arun Parikh
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Patent number: 11495461Abstract: Methods for forming a film stack comprising a hardmask layer and etching such hardmask layer to form features in the film stack are provided. The methods described herein facilitate profile and dimension control of features through a proper profile management scheme formed in the film stack. In one or more embodiments, a method for etching a hardmask layer includes forming a hardmask layer on a substrate, where the hardmask layer contains a metal-containing material containing a metal element having an atomic number greater than 28, supplying an etching gas mixture to the substrate, and etching the hardmask layer exposed by a photoresist layer.Type: GrantFiled: February 25, 2020Date of Patent: November 8, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Tejinder Singh, Suketu Arun Parikh, Daniel Lee Diehl, Michael Anthony Stolfi, Jothilingam Ramalingam, Yong Cao, Lifan Yan, Chi-I Lang, Hoyung David Hwang
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Publication number: 20220199804Abstract: A finFET device includes a doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped or p-doped source or drain extension is disposed. The doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer. After formation of the cavity, advanced processing controls (APC) (i.e., integrated metrology) is used to determine the distance of recess, without exposing the substrate to an oxidizing environment. The isotropic etch process, the metrology, and selective epitaxial growth may be performed in the same platform.Type: ApplicationFiled: March 9, 2022Publication date: June 23, 2022Applicant: Applied Materials, Inc.Inventors: Benjamin Colombeau, Tushar Mandrekar, Patricia M. Liu, Suketu Arun Parikh, Matthias Bauer, Dimitri R. Kioussis, Sanjay Natarajan, Abhishek Dube
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Publication number: 20220130722Abstract: A substrate processing method includes creating a mask on a top surface of a workpiece. A first portion of a gap fill material is overlaid by the mask and a second portion of the gap fill material is exposed through an opening in the mask. The method further includes exposing the workpiece to a plasma. The method further includes performing a first etching of the first portion of the gap fill material to create a first cavity while the second portion of the gap fill material remains in place, depositing a first metal-containing substance in the first cavity, performing a second etching of the second portion of the gap fill material to create a second cavity while the first metal-containing substance remains in place, and depositing a second metal-containing substance in the second cavity.Type: ApplicationFiled: October 19, 2021Publication date: April 28, 2022Inventors: Suketu Arun PARIKH, Martin Jay SEAMONS, Jingmei LIANG, Shuchi Sunil OJHA, Tom CHOI, Nitin K. INGLE, Sanjay NATARAJAN
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Patent number: 11309404Abstract: A finFET device includes a doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped or p-doped source or drain extension is disposed. The doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer. After formation of the cavity, advanced processing controls (APC) (i.e., integrated metrology) is used to determine the distance of recess, without exposing the substrate to an oxidizing environment. The isotropic etch process, the metrology, and selective epitaxial growth may be performed in the same platform.Type: GrantFiled: July 3, 2019Date of Patent: April 19, 2022Assignee: Applied Materials, Inc.Inventors: Benjamin Colombeau, Tushar Mandrekar, Patricia M. Liu, Suketu Arun Parikh, Matthias Bauer, Dimitri R. Kioussis, Sanjay Natarajan, Abhishek Dube
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Publication number: 20220108917Abstract: Provided are methods of forming vias with decreased resistance by selectively depositing a barrier layer on an insulating layer and not on a metallic surface. Some embodiments of the disclosure utilize a planar hydrocarbon to form a blocking layer on metallic surfaces. Deposition is performed to selectively deposit on the unblocked insulating surfaces.Type: ApplicationFiled: September 28, 2021Publication date: April 7, 2022Applicant: Applied Materials, Inc.Inventors: Roey Shaviv, Suketu Arun Parikh, Feng Chen, Lu Chen
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Patent number: 11270914Abstract: Electronic devices and methods to form electronic devices having a self-aligned via are described. An adhesion enhancement layer is utilized to promote adhesion between the conductive material and the sidewalls of the at least one via opening. The self-aligned vias decrease via resistance and reduce the potential to short to the wrong metal line.Type: GrantFiled: January 14, 2021Date of Patent: March 8, 2022Assignee: Applied Materials Inc.Inventors: Suketu Arun Parikh, Mihaela Balseanu
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Publication number: 20220068917Abstract: Logic devices and methods of forming logic devices are described. An epitaxial channel is formed orthogonally to a horizontal plane of a substrate surface with a stack or horizontal transistors on the substrate surface. The first horizontal transistor having a first length and a first step, the second horizontal transistor having a second length and a second step and a third horizontal transistor has a third length and a third step. Each of the horizontal transistors is separated from adjacent layers by a horizontal isolation layer.Type: ApplicationFiled: October 13, 2021Publication date: March 3, 2022Applicant: Applied Materials, Inc.Inventors: Suketu Arun Parikh, Sanjay Natarajan
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Publication number: 20210404062Abstract: Apparatus and methods to process one or more wafers are described. A substrate is exposed to a plurality of process stations to deposit, anneal, treat and optionally etch a film in small increments to provide self-aligned growth of the film on a substrate surface.Type: ApplicationFiled: September 14, 2021Publication date: December 30, 2021Applicant: Applied Materials, Inc.Inventor: Suketu Arun Parikh
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Publication number: 20210404061Abstract: Apparatus and methods to process one or more wafers are described. A substrate is exposed to a plurality of process stations to deposit, anneal, treat and optionally etch a film in small increments to provide self-aligned growth of the film on a substrate surface.Type: ApplicationFiled: September 14, 2021Publication date: December 30, 2021Applicant: Applied Materials, Inc.Inventor: Suketu Arun Parikh
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Publication number: 20210375637Abstract: Embodiments provided herein generally relate to methods of modifying portions of layer stacks. The methods include forming deep trenches and narrow trenches, such that a desirably low voltage drop between layers is achieved. A method of forming a deep trench includes etching portions of a flowable dielectric, such that a deep metal contact is disposed below the deep trench. The deep trench is selectively etched to form a modified deep trench. A method of forming a super via includes forming a super via trench through a second layer stack of a layer superstack. The methods disclosed herein allow for decreasing the resistance, and thus the voltage drop, of features in a semiconductor layer stack.Type: ApplicationFiled: March 10, 2021Publication date: December 2, 2021Inventor: Suketu Arun PARIKH
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Publication number: 20210375636Abstract: Embodiments provided herein generally relate to methods of modifying portions of layer stacks. The methods include forming deep trenches and narrow trenches, such that a desirably low voltage drop between layers is achieved. A method of forming a deep trench includes etching portions of a flowable dielectric, such that a deep metal contact is disposed below the deep trench. The deep trench is selectively etched to form a modified deep trench. A method of forming a super via includes forming a super via trench through a second layer stack of a layer superstack. The methods disclosed herein allow for decreasing the resistance, and thus the voltage drop, of features in a semiconductor layer stack.Type: ApplicationFiled: January 25, 2021Publication date: December 2, 2021Inventor: Suketu Arun PARIKH
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Patent number: 11177254Abstract: Logic devices and methods of forming logic devices are described. An epitaxial channel is formed orthogonally to a horizontal plane of a substrate surface with a stack or horizontal transistors on the substrate surface. The first horizontal transistor having a first length and a first step, the second horizontal transistor having a second length and a second step and a third horizontal transistor has a third length and a third step. Each of the horizontal transistors is separated from adjacent layers by a horizontal isolation layer.Type: GrantFiled: October 11, 2019Date of Patent: November 16, 2021Assignee: Applied Materials, Inc.Inventors: Suketu Arun Parikh, Sanjay Natarajan