Patents by Inventor Suketu Arun Parikh

Suketu Arun Parikh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210305087
    Abstract: A method for etching a metal containing feature is provided. Using a pattern mask, layers of material are etched to expose a portion of a metal containing feature. At least a portion of the exposed metal containing feature is etched, and is replaced by the growth of a filler dielectric. The etched portion of the metal containing feature and the filler dielectric reduce the unwanted conductivity between adjacent metal containing features.
    Type: Application
    Filed: June 10, 2021
    Publication date: September 30, 2021
    Inventor: Suketu Arun Parikh
  • Patent number: 11131022
    Abstract: Apparatus and methods to process one or more wafers are described. A substrate is exposed to a plurality of process stations to deposit, anneal, treat and optionally etch a film in small increments to provide self-aligned growth of the film on a substrate surface.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: September 28, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventor: Suketu Arun Parikh
  • Patent number: 11054815
    Abstract: Techniques are provided for classifying runs of a recipe within a manufacturing environment. Embodiments monitor a plurality of runs of a recipe to collect runtime data from a plurality of sensors within a manufacturing environment. Qualitative data describing each semiconductor devices produced by the plurality of runs is determined. Embodiments characterize each run into a respective group, based on an analysis of the qualitative data, and generate a data model based on the collected runtime data. A multivariate analysis of additional runtime data collected during at least one subsequent run of the recipe is performed to classify the at least one subsequent run into a first group. Upon classifying the at least one subsequent run, embodiments output for display an interface depicting a ranking sensor types based on the additional runtime data and the description of relative importance of each sensor type for the first group within the data model.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: July 6, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Bradley D. Schulze, Suketu Arun Parikh, Jimmy Iskandar, Jigar Bhadriklal Patel
  • Publication number: 20210166973
    Abstract: Electronic devices and methods to form electronic devices having a self-aligned via are described. An adhesion enhancement layer is utilized to promote adhesion between the conductive material and the sidewalls of the at least one via opening. The self-aligned vias decrease via resistance and reduce the potential to short to the wrong metal line.
    Type: Application
    Filed: January 14, 2021
    Publication date: June 3, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Suketu Arun Parikh, Mihaela A. Balseanu
  • Patent number: 10923396
    Abstract: Electronic devices and methods to form electronic devices having a self-aligned via are described. An adhesion enhancement layer is utilized to promote adhesion between the conductive material and the sidewalls of the at least one via opening. The self-aligned vias decrease via resistance and reduce the potential to short to the wrong metal line.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: February 16, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Suketu Arun Parikh, Mihaela Balseanu
  • Publication number: 20200273705
    Abstract: Methods for forming a film stack comprising a hardmask layer and etching such hardmask layer to form features in the film stack are provided. The methods described herein facilitate profile and dimension control of features through a proper profile management scheme formed in the film stack. In one or more embodiments, a method for etching a hardmask layer includes forming a hardmask layer on a substrate, where the hardmask layer contains a metal-containing material containing a metal element having an atomic number greater than 28, supplying an etching gas mixture to the substrate, and etching the hardmask layer exposed by a photoresist layer.
    Type: Application
    Filed: February 25, 2020
    Publication date: August 27, 2020
    Inventors: Tejinder SINGH, Suketu Arun PARIKH, Daniel Lee DIEHL, Michael Anthony STOLFI, Jothilingam RAMALINGAM, Yong CAO, Lifan YAN, Chi-I LANG, Hoyung David HWANG
  • Publication number: 20200219768
    Abstract: Electronic devices and methods to form electronic devices having a self-aligned via are described. An adhesion enhancement layer is utilized to promote adhesion between the conductive material and the sidewalls of the at least one via opening. The self-aligned vias decrease via resistance and reduce the potential to short to the wrong metal line.
    Type: Application
    Filed: March 13, 2020
    Publication date: July 9, 2020
    Inventors: Suketu Arun Parikh, Mihaela Balseanu
  • Patent number: 10695804
    Abstract: Embodiments described herein relate to a cleaning device and methods for cleaning an object. In one embodiment, the object is cleaned by moving a clean head along a surface of the object. Supercritical carbon dioxide fluid is delivered by supercritical carbon dioxide fluid vessel to the surface of the object. The supercritical carbon dioxide fluid and contamination material are removed from the object by a vacuum pump to a detector. One or more measurements of the contamination material are determined by the detector. Samples of the contamination material are collected by a collector. A contamination level of the surface of the object is determined by an analyzer.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: June 30, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Roman M. Mostovoy, Suketu Arun Parikh, Todd Egan
  • Publication number: 20200144117
    Abstract: Electronic devices and methods to form electronic devices having a self-aligned via are described. An adhesion enhancement layer is utilized to promote adhesion between the conductive material and the sidewalls of the at least one via opening. The self-aligned vias decrease via resistance and reduce the potential to short to the wrong metal line.
    Type: Application
    Filed: November 1, 2018
    Publication date: May 7, 2020
    Inventors: Suketu Arun Parikh, Mihaela Balseanu
  • Patent number: 10629484
    Abstract: Electronic devices and methods to form electronic devices having a self-aligned via are described. An adhesion enhancement layer is utilized to promote adhesion between the conductive material and the sidewalls of the at least one via opening. The self-aligned vias decrease via resistance and reduce the potential to short to the wrong metal line.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: April 21, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Suketu Arun Parikh, Mihaela Balseanu
  • Publication number: 20200118996
    Abstract: Logic devices and methods of forming logic devices are described. An epitaxial channel is formed orthogonally to a horizontal plane of a substrate surface with a stack or horizontal transistors on the substrate surface. The first horizontal transistor having a first length and a first step, the second horizontal transistor having a second length and a second step and a third horizontal transistor has a third length and a third step. Each of the horizontal transistors is separated from adjacent layers by a horizontal isolation layer.
    Type: Application
    Filed: October 11, 2019
    Publication date: April 16, 2020
    Inventors: Suketu Arun Parikh, Sanjay Natarajan
  • Publication number: 20200013878
    Abstract: A finFET device includes a doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped or p-doped source or drain extension is disposed. The doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer. After formation of the cavity, advanced processing controls (APC) (i.e., integrated metrology) is used to determine the distance of recess, without exposing the substrate to an oxidizing environment. The isotropic etch process, the metrology, and selective epitaxial growth may be performed in the same platform.
    Type: Application
    Filed: July 3, 2019
    Publication date: January 9, 2020
    Inventors: Benjamin Colombeau, Tushar Mandrekar, Patricia M. Liu, Suketu Arun Parikh, Matthias Bauer, Dimitri R. Kioussis, Sanjay Natarajan, Abhishek Dube
  • Publication number: 20190352776
    Abstract: Apparatus and methods to process one or more wafers are described. A substrate is exposed to a plurality of process stations to deposit, anneal, treat and optionally etch a film in small increments to provide self-aligned growth of the film on a substrate surface.
    Type: Application
    Filed: May 15, 2019
    Publication date: November 21, 2019
    Inventor: Suketu Arun Parikh
  • Publication number: 20190224723
    Abstract: Embodiments described herein relate to a cleaning device and methods for cleaning an object. In one embodiment, the object is cleaned by moving a clean head along a surface of the object. Supercritical carbon dioxide fluid is delivered by supercritical carbon dioxide fluid vessel to the surface of the object. The supercritical carbon dioxide fluid and contamination material are removed from the object by a vacuum pump to a detector. One or more measurements of the contamination material are determined by the detector. Samples of the contamination material are collected by a collector. A contamination level of the surface of the object is determined by an analyzer.
    Type: Application
    Filed: January 25, 2018
    Publication date: July 25, 2019
    Inventors: Roman M. MOSTOVOY, Suketu Arun PARIKH, Todd EGAN
  • Publication number: 20170261971
    Abstract: Techniques are provided for classifying runs of a recipe within a manufacturing environment. Embodiments monitor a plurality of runs of a recipe to collect runtime data from a plurality of sensors within a manufacturing environment. Qualitative data describing each semiconductor devices produced by the plurality of runs is determined. Embodiments characterize each run into a respective group, based on an analysis of the qualitative data, and generate a data model based on the collected runtime data. A multivariate analysis of additional runtime data collected during at least one subsequent run of the recipe is performed to classify the at least one subsequent run into a first group. Upon classifying the at least one subsequent run, embodiments output for display an interface depicting a ranking sensor types based on the additional runtime data and the description of relative importance of each sensor type for the first group within the data model.
    Type: Application
    Filed: March 13, 2017
    Publication date: September 14, 2017
    Inventors: Bradley D. SCHULZE, Suketu Arun PARIKH, Jimmy ISKANDAR, Jigar Bhadriklal PATEL
  • Patent number: 9184333
    Abstract: A fabrication line includes a texturizing module configured to texture a substrate, an emitter module configured to form an emitter region, a passivation layer module configured to form a passivation layer, a barrier contact module configured to form a barrier contact region, a firing module configured to anneal the barrier contact region, a top metal contact module configured to form a top metal contact region, and a soldering module configured to solder the barrier contact region to the top metal contact region. The modules are integrated by one or more automated substrate handlers into a single fabrication line. A method for fabricating a solar cell includes sequentially, in an automated fabrication line: doping a dopant in a substrate; disposing a passivation layer; disposing and annealing a barrier metal paste to form a barrier contact; and disposing and annealing a metal contact paste to form a top metal contact region.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: November 10, 2015
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Suketu Arun Parikh, Jen Shu, James M. Gee
  • Patent number: 8849438
    Abstract: A factory control server stores module configuration data for modules. The modules include processes for producing a final product and have corresponding module requirements. The factory control server analyzes in real-time actual product output data that is generated by a final product tester after a factory produces at least one final product to determine whether the actual product output data meets an expected product output. The factory control server analyzes actual module data in real-time to determine a new module requirement to cause new actual product output data for a subsequent final product to meet the expected product output in response to a determination that the actual product output data does not meet the expected product output. The factory control server notifies a module controller in real-time of the new module requirement. The module controller changes parameters in real-time to manufacture the subsequent final product.
    Type: Grant
    Filed: November 17, 2011
    Date of Patent: September 30, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Suketu Arun Parikh, Alexander T. Schwarm, Sanjiv Mittal, Charles Gay
  • Publication number: 20130288424
    Abstract: A fabrication line includes a texturizing module configured to texture a substrate, an emitter module configured to form an emitter region, a passivation layer module configured to form a passivation layer, a barrier contact module configured to form a barrier contact region, a firing module configured to anneal the barrier contact region, a top metal contact module configured to form a top metal contact region, and a soldering module configured to solder the barrier contact region to the top metal contact region. The modules are integrated by one or more automated substrate handlers into a single fabrication line. A method for fabricating a solar cell includes sequentially, in an automated fabrication line: doping a dopant in a substrate; disposing a passivation layer; disposing and annealing a barrier metal paste to form a barrier contact; and disposing and annealing a metal contact paste to form a top metal contact region.
    Type: Application
    Filed: March 8, 2013
    Publication date: October 31, 2013
    Inventors: Suketu Arun PARIKH, Jen SHU, James M. GEE
  • Patent number: 8476695
    Abstract: A method of forming a sub-lithographic charge storage element on a semiconductor substrate is provided. The method can involve providing first and second layers on a semiconductor substrate, a thickness of the first layer being larger than a thickness of the second layer; forming a spacer adjacent a side surface of the first layer and on a portion of an upper surface of the second layer; and removing an exposed portion of the second layer that is not covered by the spacer. By removing the exposed portion of the second layer while leaving a portion of the second layer that is protected by the spacer, the method can make a sub-lithographic charge storage element from the remaining portion of the second layer on the semiconductor substrate.
    Type: Grant
    Filed: February 1, 2010
    Date of Patent: July 2, 2013
    Assignee: Spansion LLC
    Inventor: Suketu Arun Parikh
  • Patent number: 8409952
    Abstract: A method of forming an electronic device including forming a first trench in a workpiece including a substrate, the first trench having side walls and a bottom surface extending for a width between the side walls and forming a charge-storage layer along the side walls and bottom surface of the first trench. The method further includes implanting ions within the substrate underlying the bottom surface of the first trench to form an implant region and annealing the implant region, wherein after annealing, the implant region extends the width of the bottom surface and along a portion of the side walls.
    Type: Grant
    Filed: April 14, 2008
    Date of Patent: April 2, 2013
    Assignee: Spansion LLC
    Inventors: Suketu Arun Parikh, Olov B. Karlsson, Yun Sun, Shankar Sinha, Timothy Thurgate