Patents by Inventor Suketu Arun Parikh

Suketu Arun Parikh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120130520
    Abstract: A factory control server stores module configuration data for modules. The modules include processes for producing a final product and have corresponding module requirements. The factory control server analyzes in real-time actual product output data that is generated by a final product tester after a factory produces at least one final product to determine whether the actual product output data meets an expected product output. The factory control server analyzes actual module data in real-time to determine a new module requirement to cause new actual product output data for a subsequent final product to meet the expected product output in response to a determination that the actual product output data does not meet the expected product output. The factory control server notifies a module controller in real-time of the new module requirement. The module controller changes parameters in real-time to manufacture the subsequent final product.
    Type: Application
    Filed: November 17, 2011
    Publication date: May 24, 2012
    Inventors: Suketu Arun Parikh, Alexander T. Schwarm, Sanjiv Mittal, Charles Gay
  • Patent number: 7781154
    Abstract: A method for forming a damascene structure utilizes dual hard mask layers and a thin etch stop layer, and does not require a sacrificial layer within the via. A floating etch stop layer can additionally be used. The dual hard masks may be formed of dielectric and neither of the hard masks is required to contain metal. The thin etch stop layer reduces capacitance problems.
    Type: Grant
    Filed: March 28, 2006
    Date of Patent: August 24, 2010
    Assignee: Applied Materials, Inc.
    Inventor: Suketu Arun Parikh
  • Publication number: 20100133605
    Abstract: A method of forming a sub-lithographic charge storage element on a semiconductor substrate is provided. The method can involve providing first and second layers on a semiconductor substrate, a thickness of the first layer being larger than a thickness of the second layer; forming a spacer adjacent a side surface of the first layer and on a portion of an upper surface of the second layer; and removing an exposed portion of the second layer that is not covered by the spacer. By removing the exposed portion of the second layer while leaving a portion of the second layer that is protected by the spacer, the method can make a sub-lithographic charge storage element from the remaining portion of the second layer on the semiconductor substrate.
    Type: Application
    Filed: February 1, 2010
    Publication date: June 3, 2010
    Applicant: SPANSION LLC
    Inventor: Suketu Arun Parikh
  • Patent number: 7682905
    Abstract: A method of forming a sub-lithographic charge storage element on a semiconductor substrate is provided. The method can involve providing first and second layers on a semiconductor substrate, a thickness of the first layer being larger than a thickness of the second layer; forming a spacer adjacent a side surface of the first layer and on a portion of an upper surface of the second layer; and removing an exposed portion of the second layer that is not covered by the spacer. By removing the exposed portion of the second layer while leaving a portion of the second layer that is protected by the spacer, the method can make a sub-lithographic charge storage element from the remaining portion of the second layer on the semiconductor substrate.
    Type: Grant
    Filed: May 9, 2007
    Date of Patent: March 23, 2010
    Assignee: Spansion LLC
    Inventor: Suketu Arun Parikh
  • Publication number: 20090256242
    Abstract: A method of forming an electronic device including forming a first trench in a workpiece including a substrate, the first trench having side walls and a bottom surface extending for a width between the side walls and forming a charge-storage layer along the side walls and bottom surface of the first trench. The method further includes implanting ions within the substrate underlying the bottom surface of the first trench to form an implant region and annealing the implant region, wherein after annealing, the implant region extends the width of the bottom surface and along a portion of the side walls.
    Type: Application
    Filed: April 14, 2008
    Publication date: October 15, 2009
    Applicant: SPANSION LLC
    Inventors: Suketu Arun Parikh, Olov B. Karlsson, Yu Sun, Shankar Sinha, Timothy Thurgate
  • Publication number: 20080280410
    Abstract: A method of forming a sub-lithographic charge storage element on a semiconductor substrate is provided. The method can involve providing first and second layers on a semiconductor substrate, a thickness of the first layer being larger than a thickness of the second layer; forming a spacer adjacent a side surface of the first layer and on a portion of an upper surface of the second layer; and removing an exposed portion of the second layer that is not covered by the spacer. By removing the exposed portion of the second layer while leaving a portion of the second layer that is protected by the spacer, the method can make a sub-lithographic charge storage element from the remaining portion of the second layer on the semiconductor substrate.
    Type: Application
    Filed: May 9, 2007
    Publication date: November 13, 2008
    Applicant: SPANSION LLC
    Inventor: Suketu Arun Parikh