Abstract: A method of making a substrate for a semiconductor package includes providing a laminated layer structure including a backing layer and a metal layer attached to the backing layer. A circuit layer is plated atop a first surface of the metal layer to form a circuit-on-metal structure. The circuit-on-metal structure is coupled to a dielectric layer by causing the dielectric layer to flow around the circuit layer to the first surface of the metal layer so that the circuit layer is embedded within the dielectric layer and the first surface of the metal layer is in direct contact with a first surface of the dielectric layer. The backing layer is then removed completely. The metal layer is then removed completely.

Abstract: A method of forming an electronic component package includes coupling a first surface of an electronic component to a first surface of a first dielectric strip, the electronic component comprising bond pads on the first surface; forming first via apertures through the first dielectric strip to expose the bond pads; and filling the first via apertures with an electrically conductive material to form first vias electrically coupled to the bond pads. The bond pads are directly connected to the corresponding first vias without the use of a solder and without the need to form a solder wetting layer on the bond pads.

Abstract: In accordance with one embodiment, a method of forming a protruding post substrate package includes applying a dielectric layer to a carrier. Via apertures are formed in the dielectric layer. Carrier cavities are formed in the carrier using the dielectric layer as a mask. The carrier cavities are lined with a first metal, the first metal being selectively etchable compared to the carrier. After encapsulation of an electronic component with an encapsulant, the carrier is removed such that protruding posts including the first metal protrude outward from a first surface of the dielectric layer.

Abstract: A method of forming an electronic component package includes coupling a first surface of an electronic component to a first surface of a first dielectric strip, the electronic component comprising bond pads on the first surface; forming first via apertures through the first dielectric strip to expose the bond pads; and filling the first via apertures with an electrically conductive material to form first vias electrically coupled to the bond pads. The bond pads are directly connected to the corresponding first vias without the use of a solder and without the need to form a solder wetting layer on the bond pads.

Abstract: A semiconductor package including top-surface terminals for mounting another semiconductor package provides a three-dimensional circuit configuration that can provide removable connection of existing grid-array packages having a standard design. A semiconductor die is mounted on an electrically connected to a circuit substrate having terminals disposed on a bottom side for connection to an external system. The die and substrate are encapsulated and vias are laser-ablated or otherwise formed through the encapsulation to terminals on the top surface of the substrate that provide a grid array mounting lands to which another grid array semiconductor package may be mounted. The bottom side of the vias may terminate and electrically connect to terminals on the substrate, terminals on the bottom of the semiconductor package (through terminals) or terminals on the top of the semiconductor die.

Abstract: A semiconductor package including top-surface terminals for mounting another semiconductor package provides a three-dimensional circuit configuration that can provide removable connection of existing grid-array packages having a standard design. A semiconductor die is mounted on an electrically connected to a circuit substrate having terminals disposed on a bottom side for connection to an external system. The die and substrate are encapsulated and vias are laser-ablated or otherwise formed through the encapsulation to terminals on the top surface of the substrate that provide a grid array mounting lands to which another grid array semiconductor package may be mounted. The bottom side of the vias may terminate and electrically connect to terminals on the substrate, terminals on the bottom of the semiconductor package (through terminals) or terminals on the top of the semiconductor die.

Abstract: A method of forming a package includes forming a circuit pattern on a first carrier and embedding the circuit pattern in a dielectric material on a second carrier. The first carrier is removed and a buildup dielectric material is mounted to the dielectric material and the circuit pattern. Laser-ablated artifacts are formed in the buildup dielectric material and filled with an electrically conductive material to form a buildup circuit pattern. The second carrier is patterned into a stiffener, which provides rigidity to the thin package.

Abstract: A method of forming an embedded electronic component package includes coupling a substrate to a first dielectric layer, strip, or panel, and forming first electrically conductive vias and traces in the first dielectric layer. A cavity is then formed in the first dielectric layer and an electronic component is attached in the cavity. A second dielectric layer, strip, or panel, is then applied to the first dielectric layer, thereby encasing the electronic component in dielectric. Second via apertures are then formed through the second dielectric layer to expose selected electronic component bond pads and/or selected first electrically conductive vias and traces. The second via apertures are then filled with an electrically conductive material to form second electrically conductive vias electrically coupled to selected bond pads and selected first electrically conductive vias and traces.

Abstract: A method of forming an embedded passive component network substrate includes providing a first carrier with a first dielectric layer and patterning the first dielectric layer to form a first patterned dielectric layer including circuit pattern artifacts. A first etch stop layer is plated within the circuit pattern artifacts. A first conductor layer is plated on the first etch stop layer and within the circuit pattern artifacts. The first etch stop layer and the first conductor layer form a first etch stop metal protected circuit pattern comprising a passive component embedded with the first patterned dielectric layer.

Abstract: A method of forming an electronic component package includes forming a patterned dielectric layer comprising circuit pattern artifacts and at least one electronic component opening. An etch stop metal protected circuit pattern is plated with the circuit pattern artifacts. An electronic component is mounted in the electronic component opening. The etch stop metal protected circuit pattern provide an etch stop for substrate formation etch processes. In this manner, etching of a patterned conductor layer is avoided insuring that impedance is controlled to within tight tolerance.

Abstract: A method of forming an electronic component package includes coupling a first surface of an electronic component to a first surface of a first dielectric strip, the electronic component comprising bond pads on the first surface; forming first via apertures through the first dielectric strip to expose the bond pads; and filling the first via apertures with an electrically conductive material to form first vias electrically coupled to the bond pads. The bond pads are directly connected to the corresponding first vias without the use of a solder and without the need to form a solder wetting layer on the bond pads.

Abstract: A first patterned etch stop layer and a first patterned conductor layer are laminated by a dielectric material to a second patterned etch stop layer and a second patterned conductor layer. As the etch stop metal of the first and second patterned etch stop layers is selectively etchable compared to a conductor metal of the first and second patterned conductor layers, the first and second patterned etch stop layers provide an etch stop for substrate formation etch processes. In this manner, etching of the first and second patterned conductor layers is avoided insuring that impedance is controlled to within tight tolerance.

Abstract: A method and structure for creating embedded metal features includes embedded trace substrates wherein bias and signal traces are embedded in a first surface of the embedded trace substrate and extend into the body of the embedded trace substrate. The bias trace and signal trace trenches are formed into the substrate body using LASER ablation, or other ablation, techniques. Using ablation techniques to form the bias and signal trace trenches allows for extremely accurate control of the depth, width, shape, and horizontal displacement of the bias and signal trace trenches. As a result, the distance between the bias traces and the signal traces eventually formed in the trenches, and therefore the electrical properties, such as impedance and noise shielding, provided by the bias traces, can be very accurately controlled.

Abstract: A method includes forming a substrate layer, the substrate layer including a circuit pattern having terminals and bump pads. A stiffener is formed, the stiffener including via apertures having electrically conductive via aperture sidewalls and an electronic component opening. The stiffener is attached to the substrate layer. The electrically conductive via aperture sidewalls are electrically connected to the terminals. An electronic component is mounted to the bump pads and within the electronic component opening thus minimizing the height of the package. Further, the stiffener minimizing undesirable bending of the package and acts as an internal heat sink.

Abstract: A method includes forming a patterned sacrificial layer on a first carrier and a patterned trace layer on the patterned sacrificial layer. The patterned sacrificial layer and the patterned trace layer are laminated to a dielectric material. The first carrier and the patterned sacrificial layer are removed creating sacrificial layer gaps above the patterned trace layer. The sacrificial layer gaps are filled with a trace layer isolation dielectric material. Shield trenches are laser-ablated within the dielectric material and on opposite sides of a signal trace of the patterned trace layer. The shield trenches are filled with an electrically conductive material to form shield walls. The electrically conductive material is patterned to form a shield top. The shield top, the shield walls, and a second carrier form a bias shield around the signal trace.

Abstract: A method of fabricating a substrate includes forming a first conductive layer on a dielectric layer, forming a resist layer on the first conductive layer, and forming laser-ablated artifacts through the first resist layer, through the first conductive layer, and at least partially into the dielectric layer. A second conductive layer is formed within the laser-ablated artifacts. The laser-ablated artifacts are filled to form an overfilled circuit pattern. The resist layer and the first conductive layer are removed. Further, a portion of the overfilled circuit pattern is removed to form an embedded circuit pattern embedded within the dielectric layer.

Abstract: A method of forming an electronic component package includes coupling a first surface of an electronic component to a first surface of a first dielectric strip, the electronic component comprising bond pads on the first surface; forming first via apertures through the first dielectric strip to expose the bond pads; and filling the first via apertures with an electrically conductive material to form first vias electrically coupled to the bond pads. The bond pads are directly connected to the corresponding first vias without the use of a solder and without the need to form a solder wetting layer on the bond pads.

Abstract: An integral plated semiconductor package substrate stiffener provides a low-cost and space-efficient mechanism for maintaining substrate planarity during the manufacturing process. By patterning and plating the stiffener along with the other substrate fabrication process steps, the difficulty of attaching a separate stiffener is averted. Also, the stiffener pattern can be provided around other substrate elements such as the circuit patterns and terminals, while maintaining requisite spacing. The stiffener is a two-layer metal structure, the first layer is a thin film metal layer on which a thicker outer metal layer is plated up. The two metal layers may be of different metals or alloys and the thin film metal layer may be the same layer plane that provides one of the substrate interconnect layers or may be the metal layer removed from other areas of the substrate during isolation of an embedded circuit layer.

Abstract: A semiconductor package including top-surface terminals for mounting another semiconductor package provides a three-dimensional circuit configuration that can provide removable connection of existing grid-array packages having a standard design. A semiconductor die is mounted on an electrically connected to a circuit substrate having terminals disposed on a bottom side for connection to an external system. The die and substrate are encapsulated and vias are laser-ablated or otherwise formed through the encapsulation to terminals on the top surface of the substrate that provide a grid array mounting lands to which another grid array semiconductor package may be mounted. The bottom side of the vias may terminate and electrically connect to terminals on the substrate, terminals on the bottom of the semiconductor package (through terminals) or terminals on the top of the semiconductor die.

Abstract: A method of forming a wafer level package includes attaching a laser-activated dielectric material to an integrated circuit substrate to form an assembly, the integrated circuit substrate including a plurality of electronic components having terminals on first surfaces thereof. The laser-activated dielectric material is laser activated and ablated with a laser to form laser-ablated artifacts in the laser-activated dielectric material and simultaneously to form an electrically conductive laser-activated layer lining the laser-ablated artifacts. The laser-ablated artifacts are filled using an electroless plating process in which an electrically conductive filler material is selectively plated on the laser-activated layer to form an embedded circuit pattern within the laser-activated dielectric material.