Patents by Inventor Sukianto Rusli
Sukianto Rusli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11848214Abstract: A method of manufacturing a semiconductor package includes mounting and electrically connecting a semiconductor die to a substrate. The semiconductor die and the substrate are encapsulated to form an encapsulation. Via holes are laser-ablated through the encapsulation and conductive material is deposited within the via holes to form vias. A first buildup dielectric layer is formed on the encapsulation. Laser-ablated artifacts are laser-ablated in the first buildup layer. The laser-ablated artifacts in the first buildup layer are filled with a first metal layer to form a first electrically conductive pattern in the first build up layer. The operations of forming a buildup layer, forming laser-ablated artifacts in the buildup layer, and filling the laser-ablated artifacts with an electrically conductive material to form an electrically conductive pattern can be performed any one of a number of times to achieve the desired redistribution.Type: GrantFiled: July 27, 2021Date of Patent: December 19, 2023Assignee: Amkor Technology Singapore Holding Pte. Ltd.Inventors: Ronald Patrick Huemoeller, Sukianto Rusli, David Jon Hiner
-
Publication number: 20210358770Abstract: A method of manufacturing a semiconductor package includes mounting and electrically connecting a semiconductor die to a substrate. The semiconductor die and the substrate are encapsulated to form an encapsulation. Via holes are laser-ablated through the encapsulation and conductive material is deposited within the via holes to form vias. A first buildup dielectric layer is formed on the encapsulation. Laser-ablated artifacts are laser-ablated in the first buildup layer. The laser-ablated artifacts in the first buildup layer are filled with a first metal layer to form a first electrically conductive pattern in the first build up layer. The operations of forming a buildup layer, forming laser-ablated artifacts in the buildup layer, and filling the laser-ablated artifacts with an electrically conductive material to form an electrically conductive pattern can be performed any one of a number of times to achieve the desired redistribution.Type: ApplicationFiled: July 27, 2021Publication date: November 18, 2021Inventors: Ronald Patrick Huemoeller, Sukianto Rusli, David Jon Hiner
-
Patent number: 11094560Abstract: A method of manufacturing a semiconductor package includes mounting and electrically connecting a semiconductor die to a substrate. The semiconductor die and the substrate are encapsulated to form an encapsulation. Via holes are laser-ablated through the encapsulation and conductive material is deposited within the via holes to form vias. A first buildup dielectric layer is formed on the encapsulation. Laser-ablated artifacts are laser-ablated in the first buildup layer. The laser-ablated artifacts in the first buildup layer are filled with a first metal layer to form a first electrically conductive pattern in the first build up layer. The operations of forming a buildup layer, forming laser-ablated artifacts in the buildup layer, and filling the laser-ablated artifacts with an electrically conductive material to form an electrically conductive pattern can be performed any one of a number of times to achieve the desired redistribution.Type: GrantFiled: June 27, 2017Date of Patent: August 17, 2021Assignee: Amkor Technology Singapore Holding Pte. Ltd.Inventors: Ronald Patrick Huemoeller, Sukianto Rusli, David Jon Hiner
-
Patent number: 11081370Abstract: A method of manufacturing a semiconductor package includes mounting and electrically connecting a semiconductor die to a substrate. The semiconductor die and the substrate are encapsulated to form an encapsulation. Via holes are laser-ablated through the encapsulation and conductive material is deposited within the via holes to form vias. A first buildup dielectric layer is formed on the encapsulation. Laser-ablated artifacts are laser-ablated in the first buildup layer. The laser-ablated artifacts in the first buildup layer are filled with a first metal layer to form a first electrically conductive pattern in the first build up layer. The operations of forming a buildup layer, forming laser-ablated artifacts in the buildup layer, and filling the laser-ablated artifacts with an electrically conductive material to form an electrically conductive pattern can be performed any one of a number of times to achieve the desired redistribution.Type: GrantFiled: October 28, 2019Date of Patent: August 3, 2021Assignee: Amkor Technology Singapore Holding Pte. Ltd.Inventors: Ronald Patrick Huemoeller, Sukianto Rusli, David Jon Hiner
-
Patent number: 10811277Abstract: A method of manufacturing a semiconductor package includes mounting and electrically connecting a semiconductor die to a substrate. The semiconductor die and the substrate are encapsulated to form an encapsulation. Via holes are laser-ablated through the encapsulation and conductive material is deposited within the via holes to form vias. A first buildup dielectric layer is formed on the encapsulation. Laser-ablated artifacts are laser-ablated in the first buildup layer. The laser-ablated artifacts in the first buildup layer are filled with a first metal layer to form a first electrically conductive pattern in the first build up layer. The operations of forming a buildup layer, forming laser-ablated artifacts in the buildup layer, and filling the laser-ablated artifacts with an electrically conductive material to form an electrically conductive pattern can be performed any one of a number of times to achieve the desired redistribution.Type: GrantFiled: May 31, 2019Date of Patent: October 20, 2020Assignee: Amkor Technology, Inc.Inventors: Ronald Patrick Huemoeller, Sukianto Rusli, David Jon Hiner
-
Patent number: 10665567Abstract: A method of forming an electronic component package includes coupling a first surface of an electronic component to a first surface of a first dielectric strip, the electronic component comprising bond pads on the first surface; forming first via apertures through the first dielectric strip to expose the bond pads; and filling the first via apertures with an electrically conductive material to form first vias electrically coupled to the bond pads. The bond pads are directly connected to the corresponding first vias without the use of a solder and without the need to form a solder wetting layer on the bond pads.Type: GrantFiled: January 16, 2018Date of Patent: May 26, 2020Assignee: Amkor Technology, Inc.Inventors: Ronald Patrick Huemoeller, Sukianto Rusli, David Razu
-
Publication number: 20200105631Abstract: Disclosed herein is a method for forming a semiconductor package. The method includes providing a first releasable chip carrier attached to a conductive layer. A circuit layer is formed on a surface of the conductive layer and a dielectric layer is applied over a surface of the circuit layer. A second releasable chip carrier is attached to a surface of the dielectric layer and the first releasable chip carrier is released from the conductive layer via facilitation of a first activating source. The circuitry of the circuit layer is operationally tested.Type: ApplicationFiled: September 15, 2017Publication date: April 2, 2020Inventor: Sukianto Rusli
-
Patent number: 10586746Abstract: Disclosed herein is a method for forming a semiconductor package. The method includes providing a first releasable chip carrier attached to a conductive layer. A circuit layer is formed on a surface of the conductive layer and a dielectric layer is applied over a surface of the circuit layer. A second releasable chip carrier is attached to a surface of the dielectric layer and the first releasable chip carrier is released from the conductive layer via facilitation of a first activating source. The circuitry of the circuit layer is operationally tested.Type: GrantFiled: September 15, 2017Date of Patent: March 10, 2020Assignee: Chip Solutions, LLCInventor: Sukianto Rusli
-
Publication number: 20200066547Abstract: A method of manufacturing a semiconductor package includes mounting and electrically connecting a semiconductor die to a substrate. The semiconductor die and the substrate are encapsulated to form an encapsulation. Via holes are laser-ablated through the encapsulation and conductive material is deposited within the via holes to form vias. A first buildup dielectric layer is formed on the encapsulation. Laser-ablated artifacts are laser-ablated in the first buildup layer. The laser-ablated artifacts in the first buildup layer are filled with a first metal layer to form a first electrically conductive pattern in the first build up layer. The operations of forming a buildup layer, forming laser-ablated artifacts in the buildup layer, and filling the laser-ablated artifacts with an electrically conductive material to form an electrically conductive pattern can be performed any one of a number of times to achieve the desired redistribution.Type: ApplicationFiled: October 28, 2019Publication date: February 27, 2020Inventors: Ronald Patrick Huemoeller, Sukianto Rusli, David Jon Hiner
-
Patent number: 10461006Abstract: A method of manufacturing a semiconductor package includes mounting and electrically connecting a semiconductor die to a substrate. The semiconductor die and the substrate are encapsulated to form an encapsulation. Via holes are laser-ablated through the encapsulation and conductive material is deposited within the via holes to form vias. A first buildup dielectric layer is formed on the encapsulation. Laser-ablated artifacts are laser-ablated in the first buildup layer. The laser-ablated artifacts in the first buildup layer are filled with a first metal layer to form a first electrically conductive pattern in the first build up layer. The operations of forming a buildup layer, forming laser-ablated artifacts in the buildup layer, and filling the laser-ablated artifacts with an electrically conductive material to form an electrically conductive pattern can be performed any one of a number of times to achieve the desired redistribution.Type: GrantFiled: December 23, 2014Date of Patent: October 29, 2019Assignee: Amkor Technology, Inc.Inventors: Ronald Patrick Huemoeller, Sukianto Rusli, David Jon Hiner
-
Publication number: 20190304949Abstract: A method of semiconductor packaging includes providing a plurality of substrate units including at least one good known substrate unit on a first adhesive layer of a first carrier. The method includes applying a first activating source to the first adhesive layer in situ such that the first adhesive layer releases from the at least one good known substrate unit without physical contact by an outside source to the at least one good known substrate unit. The method includes transferring the at least one good known substrate unit onto a second adhesive layer of a second carrier, attaching at least one die to the at least one good known substrate unit, and applying a second activating source to the second adhesive layer such that the second adhesive layer releases from the at least one good known substrate unit.Type: ApplicationFiled: March 29, 2019Publication date: October 3, 2019Inventor: Sukianto Rusli
-
Publication number: 20190287818Abstract: A method of manufacturing a semiconductor package includes mounting and electrically connecting a semiconductor die to a substrate. The semiconductor die and the substrate are encapsulated to form an encapsulation. Via holes are laser-ablated through the encapsulation and conductive material is deposited within the via holes to form vias. A first buildup dielectric layer is formed on the encapsulation. Laser-ablated artifacts are laser-ablated in the first buildup layer. The laser-ablated artifacts in the first buildup layer are filled with a first metal layer to form a first electrically conductive pattern in the first build up layer. The operations of forming a buildup layer, forming laser-ablated artifacts in the buildup layer, and filling the laser-ablated artifacts with an electrically conductive material to form an electrically conductive pattern can be performed any one of a number of times to achieve the desired redistribution.Type: ApplicationFiled: May 31, 2019Publication date: September 19, 2019Inventors: Ronald Patrick Huemoeller, Sukianto Rusli, David Jon Hiner
-
Patent number: 10354907Abstract: A method for making a semiconductor device includes providing a releasable carrier attached to a conductive layer, patterning a conductive circuit on a surface of the conductive layer, applying an insulative material at least partially covering the conductive circuit, releasing the releasable carrier from the conductive layer, and facilitating the releasing with an activating source. A method of fabricating a releasable carrier includes providing a supporting carrier, attaching a releasable tape to the supporting carrier, providing a first conductive layer and a second conductive layer attached to the first conductive layer, and attaching the first conductive layer to the releasable tape, where the releasable tape is configured to release the supporting carrier from the first conductive layer after being exposed to an activating source.Type: GrantFiled: May 11, 2018Date of Patent: July 16, 2019Assignee: CHIP SOLUTIONS, LLCInventor: Sukianto Rusli
-
Patent number: 10332775Abstract: Disclosed herein is a releasable carrier that includes a supporting carrier, a carrier conductive layer, and a releasable tape located between the supporting carrier and the carrier conductive layer. The releasable tape attaches the supporting carrier to the carrier conductive layer. The releasable tape is configured to release the supporting carrier from the carrier conductive layer after being exposed to an activating source. The releasable carrier further includes a thin conductive layer attached to the carrier conductive layer, the thin conductive layer creating a surface configured to receive a conductive circuit. Further disclosed is a method for fabricating the releasable carrier and a method for making a semiconductor device using the releasable carrier.Type: GrantFiled: July 15, 2016Date of Patent: June 25, 2019Assignee: CHIP SOLUTIONS, LLCInventor: Sukianto Rusli
-
Publication number: 20190189561Abstract: A semiconductor device includes a semiconductor die and a substrate having a first surface and a second surface. The semiconductor die is attached to the second surface. The substrate includes a layer of insulative material and an embedded conductive circuit in the layer of insulative material. The embedded conductive circuit includes an etched layer of a conductive material. The etched layer of the conductive material is located on the first surface of the substrate. The etched layer of the conductive material is made of a first metallic material and the embedded conductive circuit is made of a second metallic material that is different than the first metallic material.Type: ApplicationFiled: February 19, 2019Publication date: June 20, 2019Inventor: Sukianto Rusli
-
Publication number: 20180261489Abstract: A method for making a semiconductor device includes providing a releasable carrier attached to a conductive layer, patterning a conductive circuit on a surface of the conductive layer, applying an insulative material at least partially covering the conductive circuit, releasing the releasable carrier from the conductive layer, and facilitating the releasing with an activating source. A method of fabricating a releasable carrier includes providing a supporting carrier, attaching a releasable tape to the supporting carrier, providing a first conductive layer and a second conductive layer attached to the first conductive layer, and attaching the first conductive layer to the releasable tape, where the releasable tape is configured to release the supporting carrier from the first conductive layer after being exposed to an activating source.Type: ApplicationFiled: May 11, 2018Publication date: September 13, 2018Inventor: Sukianto Rusli
-
Patent number: 9941146Abstract: Disclosed herein is a semiconductor device that includes a semiconductor die and a substrate having a first surface and a second surface. The semiconductor die is attached to the second surface. The substrate includes a layer of insulative material and at least a portion of an embedded conductive circuit in the layer of insulative material. The substrate includes an etched layer of a conductive material attached to the portion of the conductive circuit, the etched layer of the conductive material located on the first surface of the substrate.Type: GrantFiled: July 15, 2016Date of Patent: April 10, 2018Assignee: CHIP SOLUTIONS, LLCInventor: Sukianto Rusli
-
Patent number: 9922949Abstract: Disclosed herein is a semiconductor device that includes a semiconductor die and a substrate including a first surface and a second surface. The substrate includes a conductive circuit and an insulative material over the conductive circuit. The semiconductor die is attached to the second surface. The semiconductor device further includes a metal barrier layer plated onto a functional copper layer etched to form the conductive circuit. The conductive circuit has a thickness of less than or equal to 3 ?m. Further disclosed is a method of making a semiconductor device.Type: GrantFiled: January 13, 2017Date of Patent: March 20, 2018Assignee: CHIP SOLUTIONS, LLCInventor: Sukianto Rusli
-
Publication number: 20180025955Abstract: Disclosed herein is a method for forming a semiconductor package. The method includes providing a first releasable chip carrier attached to a conductive layer. A circuit layer is formed on a surface of the conductive layer and a dielectric layer is applied over a surface of the circuit layer. A second releasable chip carrier is attached to a surface of the dielectric layer and the first releasable chip carrier is released from the conductive layer via facilitation of a first activating source. The circuitry of the circuit layer is operationally tested.Type: ApplicationFiled: September 15, 2017Publication date: January 25, 2018Inventor: Sukianto Rusli
-
Patent number: 9871015Abstract: A method of forming an electronic component package includes coupling a first surface of an electronic component to a first surface of a first dielectric strip, the electronic component comprising bond pads on the first surface; forming first via apertures through the first dielectric strip to expose the bond pads; and filling the first via apertures with an electrically conductive material to form first vias electrically coupled to the bond pads. The bond pads are directly connected to the corresponding first vias without the use of a solder and without the need to form a solder wetting layer on the bond pads.Type: GrantFiled: August 1, 2016Date of Patent: January 16, 2018Assignee: AMKOR TECHNOLOGY, INC.Inventors: Ronald Patrick Huemoeller, Sukianto Rusli, David Razu