Patents by Inventor Suman Datta

Suman Datta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of forming abrupt source drain metal gate transistors
    Patent number: 7704833
    Abstract: A gate structure may be utilized as a mask to form source and drain regions. Then the gate structure may be removed to form a gap and spacers may be formed in the gap to define a trench. In the process of forming a trench into the substrate, a portion of the source drain region is removed. Then the substrate is filled back up with an epitaxial material and a new gate structure is formed thereover. As a result, more abrupt source drain junctions may be achieved.
    Type: Grant
    Filed: August 25, 2004
    Date of Patent: April 27, 2010
    Assignee: Intel Corporation
    Inventors: Nick Lindert, Suman Datta, Jack Kavalieros, Mark L. Doczy, Matthew V. Metz, Justin K. Brask, Robert S. Chau, Mark Bohr, Anand S. Murthy
  • High mobility tri-gate devices and methods of fabrication
    Publication number: 20100065888
    Abstract: A high mobility semiconductor assembly. In one exemplary aspect, the high mobility semiconductor assembly includes a first substrate having a first reference orientation located at a <110> crystal plane location on the first substrate and a second substrate formed on top of the first substrate. The second substrate has a second reference orientation located at a <100> crystal plane location on the second substrate, wherein the first reference orientation is aligned with the second reference orientation. In another exemplary aspect, the second substrate has a second reference orientation located at a <110> crystal plane location on the second substrate, wherein the second substrate is formed over the first substrate with the second reference orientation being offset to the first reference orientation by about 45 degrees.
    Type: Application
    Filed: January 12, 2006
    Publication date: March 18, 2010
    Inventors: Mohamad A. Shaheen, Brian Doyle, Suman Datta, Robert S. Chau, Peter Tolchinksy
  • Method for making a semiconductor device having a high-k dielectric layer and a metal gate electrode
    Patent number: 7671471
    Abstract: A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, then forming a trench within the first dielectric layer. After forming a second dielectric layer on the substrate, a first metal layer is formed within the trench on a first part of the second dielectric layer. A second metal layer is then formed on the first metal layer and on a second part of the second dielectric layer.
    Type: Grant
    Filed: February 14, 2008
    Date of Patent: March 2, 2010
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Jack Kavalieros, Mark L. Doczy, Uday Shah, Chris E. Barns, Matthew V. Metz, Suman Datta, Annalisa Cappellani, Robert S. Chau
  • Semiconductor device with reduced fringe capacitance
    Patent number: 7642603
    Abstract: In one embodiment of the invention, a non-planar transistor includes a gate electrode and multiple fins. A trench contact is coupled to the fins. The contact bottom is formed above the substrate and does not directly contact the substrate. The contact bottom is higher than the gate top.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: January 5, 2010
    Assignee: Intel Corporation
    Inventors: Suman Datta, Titash Rakshit, Jack T. Kavalieros, Brian S. Doyle
  • Transistor gate electrode having conductor material layer
    Patent number: 7642610
    Abstract: Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material.
    Type: Grant
    Filed: March 8, 2007
    Date of Patent: January 5, 2010
    Assignee: Intel Corporation
    Inventors: Anand Murthy, Boyan Boyanov, Suman Datta, Brian S. Doyle, Been-Yih Jin, Shaofeng Yu, Robert Chau
  • FIELD EFFECT TRANSISTOR WITH METAL SOURCE/DRAIN REGIONS
    Publication number: 20090325350
    Abstract: A semiconductor device comprising a gate electrode formed on a gate dielectric layer formed on a semiconductor film. A pair of source/drain regions are formed adjacent the channel region on opposite sides of the gate electrode. The source and drain regions each comprise a semiconductor portion adjacent to and in contact with the semiconductor channel and a metal portion adjacent to and in contact with the semiconductor portion.
    Type: Application
    Filed: May 2, 2008
    Publication date: December 31, 2009
    Inventors: Marko Radosavljevic, Suman Datta, Brian S. Doyle, Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Amian Majumdar, Robert S. Chau
  • Directing carbon nanotube growth
    Patent number: 7638169
    Abstract: Embodiments of the invention include apparatuses and methods relating to directed carbon nanotube growth using a patterned layer. In some embodiments, the patterned layer includes an inhibitor material that directs the growth of carbon nanotubes.
    Type: Grant
    Filed: March 28, 2006
    Date of Patent: December 29, 2009
    Assignee: Intel Corporation
    Inventors: Marko Radosavljevic, Jack T. Kavalieros, Amlan Majumdar, Suman Datta
  • TRANSISTOR GATE ELECTRODE HAVING CONDUCTOR MATERIAL LAYER
    Publication number: 20090315076
    Abstract: Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material.
    Type: Application
    Filed: September 2, 2009
    Publication date: December 24, 2009
    Inventors: Anand Murthy, Boyan Boyanov, Suman Datta, Brian S. Doyle, Been-Yih Jin, Shaofeng Yu, Robert Chau
  • Tensile Strained NMOS Transistor Using Group III-N Source/Drain Regions
    Publication number: 20090302350
    Abstract: Enhancement mode transistors are described where a Group III-N compound is used in the source and drain regions to place tensile strain on the channel. The source and drain regions may be raised or embedded, and fabricated in conjunction with recessed or raised compression regions for p channel transistors.
    Type: Application
    Filed: August 14, 2009
    Publication date: December 10, 2009
    Inventors: Suman Datta, Justin K. Brask, Been-Yih Jin, Jack T. Kavalieros, Mantu K. Hudait
  • Independent n-tips for multi-gate transistors
    Patent number: 7629643
    Abstract: Independent n-tips for multi-gate transistors are generally described. In one example, an apparatus includes a semiconductor fin, one or more multi-gate pull down (PD) devices coupled with the semiconductor fin, the one or more PD devices having an n-tip dopant concentration in the semiconductor fin material adjacent to the one or more PD devices, and one or more multi-gate pass gate (PG) devices coupled with the semiconductor fin, the one or more PG devices having an n-tip dopant concentration in the semiconductor fin material adjacent to the one or more PG devices, wherein the n-tip dopant concentration for the PG device is lower than the n-tip dopant concentration for the PD device.
    Type: Grant
    Filed: November 30, 2007
    Date of Patent: December 8, 2009
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Suman Datta, Jack T. Kavalieros, Brian S. Doyle
  • DOPANT CONFINEMENT IN THE DELTA DOPED LAYER USING A DOPANT SEGREGRATION BARRIER IN QUANTUM WELL STRUCTURES
    Publication number: 20090298266
    Abstract: A device grade III-V quantum well structure and method of manufacture is described. Embodiments of the present invention enable III-V InSb quantum well device layers with defect densities below 1×108 cm?2 to be formed. In an embodiment of the present invention, a delta doped layer is disposed on a dopant segregation barrier in order to confine delta dopant within the delta doped layer and suppress delta dopant surface segregation.
    Type: Application
    Filed: August 10, 2009
    Publication date: December 3, 2009
    Inventors: Mantu K. Hudait, Aaron A. Budrevich, Dmitri Loubychev, Jack T. Kavalieros, Suman Datta, Joel M. Fastenau, Amy W. Liu
  • DIRECTING CARBON NANOTUBE GROWTH
    Publication number: 20090283496
    Abstract: Embodiments of the invention include apparatuses and methods relating to directed carbon nanotube growth using a patterned layer. In some embodiments, the patterned layer includes an inhibitor material that directs the growth of carbon nanotubes.
    Type: Application
    Filed: March 28, 2006
    Publication date: November 19, 2009
    Inventors: Marko Radosavljevic, Jack T. Kavalieros, Amlan Majumdar, Suman Datta
  • CMOS DEVICE WITH METAL AND SILICIDE GATE ELECTRODES AND A METHOD FOR MAKING IT
    Publication number: 20090280608
    Abstract: A semiconductor device and a method for forming it are described. The semoiconductor device comprises a metal NMOS gate electrode that is formed on a first part of a substrate, and a silicide PMOS gate electrode that is formed on a second part of the substrate.
    Type: Application
    Filed: November 2, 2006
    Publication date: November 12, 2009
    Inventors: Justin K. Brask, Mark L. Doczy, Jack Kavalieros, Matthew V. Metz, Chris E. Barns, Uday Shah, Suman Datta, Christopher D. Thomas, Robert S. Chau
  • Forming high-k dielectric layers on smooth substrates
    Patent number: 7615441
    Abstract: A buffer layer and a high-k metal oxide dielectric may be formed over a smooth silicon substrate. The substrate smoothness may reduce column growth of the high-k metal oxide gate dielectric. The surface of the substrate may be saturated with hydroxyl terminations prior to deposition.
    Type: Grant
    Filed: November 29, 2007
    Date of Patent: November 10, 2009
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Jack Kavalieros, Mark L. Doczy, Matthew V. Metz, Suman Datta, Uday Shah, Gilbert Dewey, Robert S. Chau
  • Transistor for non volatile memory devices having a carbon nanotube channel and electrically floating quantum dots in its gate dielectric
    Patent number: 7608883
    Abstract: A transistor is described having a source electrode and a drain electrode. The transistor has at least one semiconducting carbon nanotube that is electrically coupled between the source and drain electrodes. The transistor has a gate electrode and dielectric material containing one or more quantum dots between the carbon nanotube and the gate electrode.
    Type: Grant
    Filed: February 28, 2008
    Date of Patent: October 27, 2009
    Assignee: Intel Corporation
    Inventors: Marko Radosavljevic, Amlan Majumdar, Suman Datta, Justin Brask, Brian Doyle, Robert Chau
  • Complementary Metal Oxide Semiconductor Integrated Circuit Using Raised Source Drain and Replacement Metal Gate
    Publication number: 20090261391
    Abstract: A complementary metal oxide semiconductor integrated circuit may be formed with a PMOS device formed using a replacement metal gate and a raised source drain. The raised source drain may be formed of epitaxially deposited silicon germanium material that is doped p-type. The replacement metal gate process results in a metal gate electrode and may involve the removal of a nitride etch stop layer.
    Type: Application
    Filed: June 29, 2009
    Publication date: October 22, 2009
    Inventors: Jack KAVALIEROS, Annalisa CAPPELLANI, Justin K. BRASK, Mark L. DOCZY, Matthew V. METZ, Suman DATTA, Chris E. BARNS, Robert S. CHAU
  • Dopant confinement in the delta doped layer using a dopant segregation barrier in quantum well structures
    Patent number: 7601980
    Abstract: A device grade III-V quantum well structure and method of manufacture is described. Embodiments of the present invention enable III-V InSb quantum well device layers with defect densities below 1×108 cm?2 to be formed. In an embodiment of the present invention, a delta doped layer is disposed on a dopant segregation barrier in order to confine delta dopant within the delta doped layer and suppress delta dopant surface segregation.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: October 13, 2009
    Assignee: Intel Corporation
    Inventors: Mantu K. Hudait, Aaron A. Budrevich, Dmitri Loubychev, Jack T. Kavalieros, Suman Datta, Joel M. Fastenau, Amy W. K. Liu
  • Hetero-bimos injection process for non-volatile flash memory
    Patent number: 7598560
    Abstract: A hetero-BiMOS injection system comprises a MOSFET transistor formed on a substrate and a hetero-bipolar transistor formed within the substrate. The bipolar transistor can be used to inject charge carriers into a floating gate of the MOSFET transistor. This is done by operating the MOSFET transistor to form an inversion layer in its channel region and operating the bipolar transistor to drive minority charge carriers from the substrate into a floating gate of the MOSFET transistor. The substrate provides a silicon emitter and a silicon germanium containing base for the bipolar transistor. The inversion layer provides a silicon collector for the bipolar transistor.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: October 6, 2009
    Inventors: Jack T. Kavalieros, Suman Datta, Robert S. Chau, David L. Kencke
  • Tensile strained NMOS transistor using group III-N source/drain regions
    Patent number: 7592213
    Abstract: Enhancement mode transistors are described where a Group III-N compound is used in the source and drain regions to place tensile strain on the channel. The source and drain regions may be raised or embedded, and fabricated in conjunction with recessed or raised compression regions for p channel transistors.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: September 22, 2009
    Assignee: Intel Corporation
    Inventors: Suman Datta, Justin K. Brask, Been-Yih Jin, Jack T. Kavalieros, Mantu K. Hudait
  • SEMICONDUCTOR DEVICE STRUCTURES AND METHODS OF FORMING SEMICONDUCTOR STRUCTURES
    Publication number: 20090218603
    Abstract: A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.
    Type: Application
    Filed: May 8, 2009
    Publication date: September 3, 2009
    Inventors: Justin K. Brask, Jack Kavalieros, Uday Shah, Suman Datta, Amlan Majumdar, Robert S. Chau, Brian S. Doyle