Patents by Inventor Suman Datta

Suman Datta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Field effect transistor with narrow bandgap source and drain regions and method of fabrication
    Patent number: 7825481
    Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: November 2, 2010
    Assignee: Intel Corporation
    Inventors: Robert S. Chau, Suman Datta, Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew Metz
  • Spacer patterned augmentation of tri-gate transistor gate length
    Patent number: 7820512
    Abstract: In general, in one aspect, a method includes forming a semiconductor substrate having N-diffusion and P-diffusion regions. A gate stack is formed over the semiconductor substrate. A gate electrode hard mask is formed over the gate stack. The gate electrode hard mask is augmented around pass gate transistors with a spacer material. The gate stack is etched using the augmented gate electrode hard mask to form the gate electrodes. The gate electrodes around the pass gate have a greater length than other gate electrodes.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: October 26, 2010
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Suman Datta, Jack Kavalieros, Brian S. Doyle, Uday Shah
  • Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
    Patent number: 7820513
    Abstract: A nonplanar semiconductor device and its method of fabrication is described. The nonplanar semiconductor device includes a semiconductor body having a top surface opposite a bottom surface formed above an insulating substrate wherein the semiconductor body has a pair laterally opposite sidewalls. A gate dielectric is formed on the top surface of the semiconductor body on the laterally opposite sidewalls of the semiconductor body and on at least a portion of the bottom surface of semiconductor body. A gate electrode is formed on the gate dielectric, on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of semiconductor body and beneath the gate dielectric on the bottom surface of the semiconductor body. A pair source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.
    Type: Grant
    Filed: October 28, 2008
    Date of Patent: October 26, 2010
    Assignee: Intel Corporation
    Inventors: Scott A. Hareland, Robert S. Chau, Brian S. Doyle, Rafael Rios, Tom Linton, Suman Datta
  • ISOLATION OF MIM FIN DRAM CAPACITOR
    Publication number: 20100258908
    Abstract: In one embodiment, a capacitor comprises a substrate, a first electrically insulating layer over the substrate, a fin comprising a semiconducting material over the first electrically insulating layer, a cap formed from a suicide material on the first semiconducting fin, a first electrically conducting layer over the first electrically insulating layer and adjacent to the fin, a second electrically insulating layer adjacent to the first electrically conducting layer and a second electrically conducting layer adjacent to the second electrically insulating
    Type: Application
    Filed: June 24, 2010
    Publication date: October 14, 2010
    Inventors: BRIAN S. DOYLE, Dinesh Somasekhar, Robert S. Chau, Suman Datta
  • Three-dimensional integrated circuit for analyte detection
    Publication number: 20100248209
    Abstract: The embodiments of the invention relate to a device having a first substrate comprising a transistor; a second substrate; an insulating layer in between and adjoining the first and second substrates; and an opening within the second substrate, the opening being aligned with the transistor; wherein the transistor is configured to detect an electrical charge change within the opening. Other embodiments relate to a method including providing a substrate comprising a first part, a second part, and an insulating layer in between and adjoining the first and second parts; fabricating a transistor on the first part; and fabricating an opening within the second part, the opening being aligned with the transistor; wherein the transistor is configured to detect an electrical charge change within the opening.
    Type: Application
    Filed: June 30, 2006
    Publication date: September 30, 2010
    Inventors: Suman Datta, Shriram Ramanathan, Jack T. Kavalieros, Justin K. Brask, Brandon Barnett
  • High hole mobility p-channel Ge transistor structure on Si substrate
    Patent number: 7791063
    Abstract: The present disclosure provides an apparatus and method for implementing a high hole mobility p-channel Germanium (“Ge”) transistor structure on a Silicon (“Si”) substrate. One exemplary apparatus may include a buffer layer including a GaAs nucleation layer, a first GaAs buffer layer, and a second GaAs buffer layer. The exemplary apparatus may further include a bottom barrier on the second GaAs buffer layer and having a band gap greater than 1.1 eV, a Ge active channel layer on the bottom barrier and having a valence band offset relative to the bottom barrier that is greater than 0.3 eV, and an AlAs top barrier on the Ge active channel layer wherein the AlAs top barrier has a band gap greater than 1.1 eV. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
    Type: Grant
    Filed: August 30, 2007
    Date of Patent: September 7, 2010
    Assignee: Intel Corporation
    Inventors: Mantu K. Hudait, Suman Datta, Jack T. Kavalieros, Peter G. Tolchinsky
  • Dopant confinement in the delta doped layer using a dopant segregration barrier in quantum well structures
    Patent number: 7790536
    Abstract: A device grade III-V quantum well structure and method of manufacture is described. Embodiments of the present invention enable III-V InSb quantum well device layers with defect densities below 1×108cm?2 to be formed. In an embodiment of the present invention, a delta doped layer is disposed on a dopant segregation barrier in order to confine delta dopant within the delta doped layer and suppress delta dopant surface segregation.
    Type: Grant
    Filed: August 10, 2009
    Date of Patent: September 7, 2010
    Assignee: Intel Corporation
    Inventors: Mantu K. Hudait, Aaron A. Budrevich, Dmitri Loubychev, Jack T. Kavalieros, Suman Datta, Joel M. Fastenau, Amy W. K. Liu
  • Mechanism for Forming a Remote Delta Doping Layer of a Quantum Well Structure
    Publication number: 20100219396
    Abstract: A method of fabricating a quantum well device includes forming a diffusion barrier on sides of a delta layer of a quantum well to confine dopants to the quantum well.
    Type: Application
    Filed: March 1, 2010
    Publication date: September 2, 2010
    Inventors: Been-Yih Jin, Jack T. Kavalieros, Suman Datta, Amlan Majumdar, Robert S. Chau
  • FORMING INTEGRATED CIRCUITS WITH REPLACEMENT METAL GATE ELECTRODES
    Publication number: 20100219456
    Abstract: In a metal gate replacement process, a stack of at least two polysilicon layers or other materials may be formed. Sidewall spacers may be formed on the stack. The stack may then be planarized. Next, the upper layer of the stack may be selectively removed. Then, the exposed portions of the sidewall spacers may be selectively removed. Finally, the lower portion of the stack may be removed to form a T-shaped trench which may be filled with the metal replacement.
    Type: Application
    Filed: May 17, 2010
    Publication date: September 2, 2010
    Inventors: Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew V. Metz, Suman Datta, Uday Shah, Robert S. Chau
  • Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
    Patent number: 7785958
    Abstract: A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, a trench within the first dielectric layer, and a second dielectric layer on the substrate. The second dielectric layer has a first part that is formed in the trench and a second part. After a first metal layer with a first workfunction is formed on the first and second parts of the second dielectric layer, part of the first metal layer is converted into a second metal layer with a second workfunction.
    Type: Grant
    Filed: June 12, 2008
    Date of Patent: August 31, 2010
    Assignee: Intel Corporation
    Inventors: Mark L. Doczy, Justin K. Brask, Jack Kavalieros, Uday Shah, Matthew V. Metz, Suman Datta, Ramune Nagisetty, Robert S. Chau
  • Increasing the surface area of a memory cell capacitor
    Patent number: 7776684
    Abstract: Methods and apparatuses to increase a surface area of a memory cell capacitor are described. An opening in a second insulating layer deposited over a first insulating layer on a substrate is formed. The substrate has a fin. A first insulating layer is deposited over the substrate adjacent to the fin. The opening in the second insulating layer is formed over the fin. A first conducting layer is deposited over the second insulating layer and the fin. A third insulating layer is deposited on the first conducting layer. A second conducting layer is deposited on the third insulating layer. The second conducting layer fills the opening. The second conducting layer is to provide an interconnect to an upper metal layer. Portions of the second conducting layer, third insulating layer, and the first conducting layer are removed from a top surface of the second insulating layer.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: August 17, 2010
    Assignee: Intel Corporation
    Inventors: Brian S. Doyle, Robert S. Chau, Vivek De, Suman Datta, Dinesh Somasekhar
  • NONPLANAR DEVICE WITH STRESS INCORPORATION LAYER AND METHOD OF FABRICATION
    Publication number: 20100200917
    Abstract: A semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls is formed on an insulating substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and is formed adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. A thin film is then formed adjacent to the semiconductor body wherein the thin film produces a stress in the semiconductor body.
    Type: Application
    Filed: April 26, 2010
    Publication date: August 12, 2010
    Inventors: Scott A. Hareland, Robert S. Chau, Brian S. Doyle, Suman Datta, Been-Yih Jin
  • SUBSTRATE BAND GAP ENGINEERED MULTI-GATE PMOS DEVICES
    Publication number: 20100193840
    Abstract: A multi-gate transistor and a method of forming a multi-gate transistor, the multi-gate transistor including a fin having an upper portion and a lower portion. The upper portion having a first band gap and the lower portion having a second band gap with the first band gap and the second band gap designed to inhibit current flow from the upper portion to the lower portion. The multi-gate transistor further including a gate structure having sidewalls electrically coupled with said upper portion and said lower portion and a substrate positioned below the fin.
    Type: Application
    Filed: April 9, 2010
    Publication date: August 5, 2010
    Inventors: Brian S. Doyle, Been-Yih Jin, Jack T. Kavalieros, Suman Datta
  • INCREASING THE SURFACE AREA OF A MEMORY CELL CAPACITOR
    Publication number: 20100181607
    Abstract: Methods and apparatuses to increase a surface area of a memory cell capacitor are described. An opening in a second insulating layer deposited over a first insulating layer on a substrate is formed. The substrate has a fin. A first insulating layer is deposited over the substrate adjacent to the fin. The opening in the second insulating layer is formed over the fin. A first conducting layer is deposited over the second insulating layer and the fin. A third insulating layer is deposited on the first conducting layer. A second conducting layer is deposited on the third insulating layer. The second conducting layer fills the opening. The second conducting layer is to provide an interconnect to an upper metal layer. Portions of the second conducting layer, third insulating layer, and the first conducting layer are removed from a top surface of the second insulating layer.
    Type: Application
    Filed: March 29, 2010
    Publication date: July 22, 2010
    Inventors: Brian S. Doyle, Robert S. Chau, Vivek De, Suman Datta, Dinesh Somasekhar
  • FORMING ABRUPT SOURCE DRAIN METAL GATE TRANSISTORS
    Publication number: 20100151669
    Abstract: A gate structure may be utilized as a mask to form source and drain regions. Then the gate structure may be removed to form a gap and spacers may be formed in the gap to define a trench. In the process of forming a trench into the substrate, a portion of the source drain region is removed. Then the substrate is filled back up with an epitaxial material and a new gate structure is formed thereover. As a result, more abrupt source drain junctions may be achieved.
    Type: Application
    Filed: February 26, 2010
    Publication date: June 17, 2010
    Inventors: Nick Lindert, Suman Datta, Jack Kavalieros, Mark L. Doczy, Matthew V. Metz, Justin K. Brask, Robert S. Chau, Mark Bohr, Anand S. Murthy
  • Lateral undercut of metal gate in SOI device
    Patent number: 7736956
    Abstract: Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer, source/drain extensions a distance beneath the metal gate, and lateral undercuts in the sides of the metal gate.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: June 15, 2010
    Assignee: Intel Corporation
    Inventors: Suman Datta, Justin K. Brask, Jack Kavalieros, Brian S. Doyle, Gilbert Dewey, Mark L. Doczy, Robert S. Chau
  • Forming integrated circuits with replacement metal gate electrodes
    Patent number: 7718479
    Abstract: In a metal gate replacement process, a stack of at least two polysilicon layers or other materials may be formed. Sidewall spacers may be formed on the stack. The stack may then be planarized. Next, the upper layer of the stack may be selectively removed. Then, the exposed portions of the sidewall spacers may be selectively removed. Finally, the lower portion of the stack may be removed to form a T-shaped trench which may be filled with the metal replacement.
    Type: Grant
    Filed: August 25, 2004
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventors: Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew V. Metz, Suman Datta, Uday Shah, Robert S. Chau
  • Tri-gate transistor device with stress incorporation layer and method of fabrication
    Patent number: 7714397
    Abstract: A semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls is formed on an insulating substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and is formed adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. A thin film is then formed adjacent to the semiconductor body wherein the thin film produces a stress in the semiconductor body.
    Type: Grant
    Filed: July 25, 2006
    Date of Patent: May 11, 2010
    Assignee: Intel Corporation
    Inventors: Scott A. Hareland, Robert S. Chau, Brian S. Doyle, Suman Datta, Been-Yih Jin
  • Mechanism for forming a remote delta doping layer of a quantum well structure
    Patent number: 7713803
    Abstract: A method of fabricating a quantum well device includes forming a diffusion barrier on sides of a delta layer of a quantum well to confine dopants to the quantum well.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: May 11, 2010
    Assignee: Intel Corporation
    Inventors: Been-Yih Jin, Jack T. Kavalieros, Suman Datta, Amlan Majumdar, Robert S. Chau
  • Method for making a semiconductor device having a high-k gate dielectric
    Patent number: 7709909
    Abstract: A method for making a semiconductor device is described. That method comprises forming an oxide layer on a substrate, and forming a high-k dielectric layer on the oxide layer. The oxide layer and the high-k dielectric layer are then annealed at a sufficient temperature for a sufficient time to generate a gate dielectric with a graded dielectric constant.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: May 4, 2010
    Assignee: Intel Corporation
    Inventors: Mark L. Doczy, Gilbert Dewey, Suman Datta, Sangwoo Pae, Justin K. Brask, Jack Kavalieros, Matthew V. Metz, Adrian B. Sherrill, Markus Kuhn, Robert S. Chau