Patents by Inventor Suman Datta

Suman Datta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHOD FOR FABRICATING TRANSISTOR WITH THINNED CHANNEL
    Publication number: 20110062520
    Abstract: A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.
    Type: Application
    Filed: November 18, 2010
    Publication date: March 17, 2011
    Inventors: Justin K. Brask, Robert S. Chau, Suman Datta, Mark L. Doczy, Brian S. Doyle, Jack T. Kavalieros, Amlan Majumdar, Matthew V. Metz, Marko Radosavljevic
  • Inducing strain in the channels of metal gate transistors
    Patent number: 7902058
    Abstract: In a metal gate replacement process, strain may be selectively induced in the channels of NMOS and PMOS transistors. For example, a material having a higher coefficient of thermal expansion than the substrate may be used to form the gate electrodes of PMOS transistors. A material with a lower coefficient of thermal expansion than that of the substrate may be used to form the gate electrodes of NMOS transistors.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: March 8, 2011
    Assignee: Intel Corporation
    Inventors: Suman Datta, Jack Kavalieros, Mark L. Doczy, Matthew V. Metz, Justin K. Brask, Robert S. Chau, Brian S. Doyle
  • CMOS devices with a single work function gate electrode and method of fabrication
    Patent number: 7902014
    Abstract: Described herein are a device utilizing a gate electrode material with a single work function for both the pMOS and nMOS transistors where the magnitude of the transistor threshold voltages is modified by semiconductor band engineering and article made thereby. Further described herein are methods of fabricating a device formed of complementary (pMOS and nMOS) transistors having semiconductor channel regions which have been band gap engineered to achieve a low threshold voltage.
    Type: Grant
    Filed: January 3, 2007
    Date of Patent: March 8, 2011
    Assignee: Intel Corporation
    Inventors: Brian S. Doyle, Been-Yih Jin, Jack T. Kavalieros, Suman Datta, Justin K. Brask, Robert S. Chau
  • Block contact architectures for nanoscale channel transistors
    Patent number: 7898041
    Abstract: A contact architecture for nanoscale channel devices having contact structures coupling to and extending between source or drain regions of a device having a plurality of parallel semiconductor bodies. The contact structures being able to contact parallel semiconductor bodies having sub-lithographic pitch.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: March 1, 2011
    Assignee: Intel Corporation
    Inventors: Marko Radosavljevic, Amlan Majumdar, Brian S. Doyle, Jack Kavalieros, Mark L. Doczy, Justin K. Brask, Uday Shah, Suman Datta, Robert S. Chau
  • Field effect transistor with narrow bandgap source and drain regions and method of fabrication
    Patent number: 7893506
    Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.
    Type: Grant
    Filed: August 4, 2010
    Date of Patent: February 22, 2011
    Assignee: Intel Corporation
    Inventors: Robert S. Chau, Suman Datta, Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew Metz
  • Tunneling field effect transistor using angled implants for forming asymmetric source/drain regions
    Patent number: 7888221
    Abstract: The present invention relates to a Tunnel Field Effect Transistor (TFET), which utilizes angle implantation and amorphization to form asymmetric source and drain regions. The TFET further includes a silicon germanium alloy epitaxial source region with a conductivity opposite that of the drain.
    Type: Grant
    Filed: August 22, 2008
    Date of Patent: February 15, 2011
    Assignee: Intel Corporation
    Inventors: Jack T. Kavalieros, Matthew V. Metz, Gilbert Dewey, Been-Yih Jin, Justin K. Brask, Suman Datta, Robert S. Chau
  • CMOS device with metal and silicide gate electrodes and a method for making it
    Patent number: 7883951
    Abstract: A semiconductor device and a method for forming it are described. The semiconductor device comprises a metal NMOS gate electrode that is formed on a first part of a substrate, and a silicide PMOS gate electrode that is formed on a second part of the substrate.
    Type: Grant
    Filed: November 2, 2006
    Date of Patent: February 8, 2011
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Mark L. Doczy, Jack Kavalieros, Matthew V. Metz, Chris E. Barns, Uday Shah, Suman Datta, Christopher D. Thomas, Robert S. Chau
  • Field effect transistor with metal source/drain regions
    Patent number: 7879675
    Abstract: A semiconductor device comprising a gate electrode formed on a gate dielectric layer formed on a semiconductor film. A pair of source/drain regions are formed adjacent the channel region on opposite sides of the gate electrode. The source and drain regions each comprise a semiconductor portion adjacent to and in contact with the semiconductor channel and a metal portion adjacent to and in contact with the semiconductor portion.
    Type: Grant
    Filed: May 2, 2008
    Date of Patent: February 1, 2011
    Assignee: Intel Corporation
    Inventors: Marko Radosavljevic, Suman Datta, Brian S. Doyle, Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Amian Majumdar, Robert S. Chau
  • Thin transition layer between a group III-V substrate and a high-k gate dielectric layer
    Patent number: 7879739
    Abstract: Embodiments of the invention provide a method to form a high-k dielectric layer on a group III-V substrate with substantially no oxide of the group III-V substrate between the substrate and high-k dielectric layer. Oxide may be removed from the substrate. An organometallic compound may form a capping layer on the substrate from which the oxide was removed. The high-k dielectric layer may then be formed, resulting in a thin transition layer between the substrate and high-k dielectric layer and substantially no oxide of the group III-V substrate between the substrate and high-k dielectric layer.
    Type: Grant
    Filed: May 9, 2006
    Date of Patent: February 1, 2011
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, James Blackwell, Suman Datta, Jack T. Kavalieros, Mantu K. Hudait
  • STRAIN-INDUCING SEMICONDUCTOR REGIONS
    Publication number: 20110017978
    Abstract: A method to form a strain-inducing semiconductor region is described. In one embodiment, formation of a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In another embodiment, a semiconductor region with a crystalline lattice of one or more species of charge-neutral lattice-forming atoms imparts a strain to a crystalline substrate, wherein the lattice constant of the semiconductor region is different from that of the crystalline substrate, and wherein all species of charge-neutral lattice-forming atoms of the semiconductor region are contained in the crystalline substrate.
    Type: Application
    Filed: October 5, 2010
    Publication date: January 27, 2011
    Inventors: Suman Datta, Jack T. Kavalieros, Been-Yih Jin
  • TRANSISTOR GATE ELECTRODE HAVING CONDUCTOR MATERIAL LAYER
    Publication number: 20110018031
    Abstract: Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material.
    Type: Application
    Filed: September 29, 2010
    Publication date: January 27, 2011
    Inventors: Anand Murthy, Boyan Boyanov, Suman Datta, Brian S. Doyle, Been-Yih Jin, Shaofeng Yu, Robert Chau
  • NONPLANAR SEMICONDUCTOR DEVICE WITH PARTIALLY OR FULLY WRAPPED AROUND GATE ELECTRODE AND METHODS OF FABRICATION
    Publication number: 20110020987
    Abstract: A nonplanar semiconductor device and its method of fabrication is described. The nonplanar semiconductor device includes a semiconductor body having a top surface opposite a bottom surface formed above an insulating substrate wherein the semiconductor body has a pair laterally opposite sidewalls. A gate dielectric is formed on the top surface of the semiconductor body on the laterally opposite sidewalls of the semiconductor body and on at least a portion of the bottom surface of semiconductor body. A gate electrode is formed on the gate dielectric, on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of semiconductor body and beneath the gate dielectric on the bottom surface of the semiconductor body. A pair source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.
    Type: Application
    Filed: September 29, 2010
    Publication date: January 27, 2011
    Inventors: Scott A. Hareland, Robert S. Chau, Brian S. Doyle, Rafael Rios, Tom Linton, Suman Datta
  • Semiconductor device with a high-k gate dielectric and a metal gate electrode
    Patent number: 7875937
    Abstract: A semiconductor device is described. That semiconductor device comprises a high-k gate dielectric layer that is formed on a substrate that applies strain to the high-k gate dielectric layer, and a metal gate electrode that is formed on the high-k gate dielectric layer.
    Type: Grant
    Filed: October 7, 2008
    Date of Patent: January 25, 2011
    Assignee: Intel Corporation
    Inventors: Matthew V. Metz, Suman Datta, Mark L. Doczy, Justin K. Brask, Jack Kavalieros, Robert S. Chau
  • Transistor gate electrode having conductor material layer
    Patent number: 7871916
    Abstract: Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material.
    Type: Grant
    Filed: September 2, 2009
    Date of Patent: January 18, 2011
    Assignee: Intel Corporation
    Inventors: Anand Murthy, Boyan Boyanov, Suman Datta, Brian S. Doyle, Been-Yih Jin, Shaofeng Yu, Robert Chau
  • HIGH HOLE MOBILITY P-CHANNEL GE TRANSISTOR STRUCTURE ON SI SUBSTRATE
    Publication number: 20100327261
    Abstract: The present disclosure provides an apparatus and method for implementing a high hole mobility p-channel Germanium (“Ge”) transistor structure on a Silicon (“Si”) substrate. One exemplary apparatus may include a buffer layer including a GaAs nucleation layer, a first GaAs buffer layer, and a second GaAs buffer layer. The exemplary apparatus may further include a bottom barrier on the second GaAs buffer layer and having a band gap greater than 1.1 eV, a Ge active channel layer on the bottom barrier and having a valence band offset relative to the bottom barrier that is greater than 0.3 eV, and an AlAs top barrier on the Ge active channel layer wherein the AlAs top barrier has a band gap greater than 1.1 eV. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
    Type: Application
    Filed: September 7, 2010
    Publication date: December 30, 2010
    Applicant: INTEL CORPORATION
    Inventors: Mantu K. Hudait, Suman Datta, Jack T. Kavalieros, Peter G. Tolchinsky
  • Method for fabricating transistor with thinned channel
    Patent number: 7858481
    Abstract: A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.
    Type: Grant
    Filed: June 15, 2005
    Date of Patent: December 28, 2010
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Robert S. Chau, Suman Datta, Mark L. Doczy, Brian S. Doyle, Jack T. Kavalieros, Amlan Majumdar, Matthew V. Metz, Marko Radosavljevic
  • Capacitor, method of increasing a capacitance area of same, and system containing same
    Patent number: 7859081
    Abstract: A capacitor includes a substrate (110, 210), a first electrically insulating layer (120, 220) over the substrate, and a fin (130, 231) including a semiconducting material (135) over the first electrically insulating layer. A first electrically conducting layer (140, 810) is located over the first electrically insulating layer and adjacent to the fin. A second electrically insulating layer (150, 910) is located adjacent to the first electrically conducting layer, and a second electrically conducting layer (160, 1010) is located adjacent to the second electrically insulating layer. The first and second electrically conducting layers together with the second electrically insulating layer form a metal-insulator-metal stack that greatly increases the capacitance area of the capacitor. In one embodiment the capacitor is formed using what may be referred to as a removable metal gate (RMG) approach.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: December 28, 2010
    Assignee: Intel Corporation
    Inventors: Brian S. Doyle, Robert S. Chau, Suman Datta, Vivek De, Ali Keshavarzi, Dinesh Somasekhar
  • FIELD EFFECT TRANSISTOR WITH NARROW BANDGAP SOURCE AND DRAIN REGIONS AND METHOD OF FABRICATION
    Publication number: 20100295129
    Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.
    Type: Application
    Filed: August 4, 2010
    Publication date: November 25, 2010
    Inventors: Robert S. Chau, Suman Datta, Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew Metz
  • Unity beta ratio tri-gate transistor static random access memory (SRAM)
    Patent number: 7825437
    Abstract: In general, in one aspect, a method includes forming N-diffusion and P-diffusion fins in a semiconductor substrate. A P-diffusion gate layer is formed over the semiconductor substrate and removed from the N-diffusion fins. A pass-gate N-diffusion gate layer is formed over the semiconductor substrate and removed from the P-diffusion fins and pull-down N-diffusion fins. A pull-down N-diffusion layer is formed over the semiconductor substrate.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: November 2, 2010
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Suman Datta, Jack Kavalieros, Brian S. Doyle, Uday Shah
  • Strain-inducing semiconductor regions
    Patent number: 7825400
    Abstract: A method to form a strain-inducing semiconductor region is described. In one embodiment, formation of a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In another embodiment, a semiconductor region with a crystalline lattice of one or more species of charge-neutral lattice-forming atoms imparts a strain to a crystalline substrate, wherein the lattice constant of the semiconductor region is different from that of the crystalline substrate, and wherein all species of charge-neutral lattice-forming atoms of the semiconductor region are contained in the crystalline substrate.
    Type: Grant
    Filed: June 9, 2006
    Date of Patent: November 2, 2010
    Assignee: Intel Corporation
    Inventors: Suman Datta, Jack T. Kavalieros, Been-Yih Jin