Abstract: A system and method are used to maintain a variance in feedback factors of an amplifier between the first and second phases either below a threshold value or within a specified range. The system includes the amplifier and first through third capacitances. The amplifier is coupled between an input node and an output node that operates during first and second phases of operation. The first capacitance is coupled across the amplifier and between the input node and the output node during the first and second phases of operation. The second capacitance is coupled to the input node during the first phase of operation. The third capacitance is coupled to one of the input and output nodes during one or both of the first and second phases of operation.

Abstract: Low voltage swing pad driver and receiver. A transmitter portion and a receiver portion are implemented within various devices that communicate using low voltage swing pads communicatively coupled via a trace. The transmitter portion of one device generates a current signal that is pushed/pulled to a low voltage swing pad and is then passed across the trace to another low voltage swing pad. The transmitter portion includes a current driver that outputs the current signal to the low voltage swing pads, and the receiver portion includes a trans-impedance amplifier that transforms the received current signal into a voltage signal. The low voltage swing pad driver and receiver generates a relatively low voltage swing when compared to CMOS full-scale voltage swings thereby significantly reducing the possibility of introducing any noise and/or distortion of data that is communicated via the interface.

Abstract: An input buffer amplifier has a symmetrical centroidal layout. The input buffer amplifier includes two half differential amplifiers that have substantially identical layouts. Each half amplifier receives the input signal in-parallel, and the outputs of the differential half amplifiers are wire-ored together. The input buffer amplifier is symmetrical about both horizontal and vertical lines of symmetry. Furthermore, FET devices forming the half amplifiers are interlaced to create the horizontal line of symmetry. The overall horizontal and vertical symmetry of the input buffer amplifier improves the device matching between differential signal paths. In other words, the devices in the half amplifiers that process the positive and negative components of the differential signal are more closely matched. This reduces differential offsets and common mode offsets that can occur when devices are not matched properly.

Abstract: An operational amplifier includes a first stage with a first differential transistor pair inputting a differential input signal at their gates, a first tail current source transistor connected to sources of the first differential transistor pair, and a load transistor pair connected in series with the drain of first differential transistor pair. An input stage includes a second differential transistor pair connected to respective drains of the first differential transistor pair at their gates, and a second tail current transistor connected to sources of the differential transistor pair. An output stage outputs a signal corresponding to the differential input signal.

Abstract: A transmitter portion and a receiver portion are implemented within various devices that communicate using low voltage swing pads communicatively coupled via a trace. The transmitter portion of one device generates a current signal that is pushed/pulled to a low voltage swing pad and is then passed across the trace to another low voltage swing pad. The transmitter portion includes a current driver that outputs the current signal to the low voltage swing pads, and the receiver portion includes a trans-impedance amplifier that transforms the received current signal into a voltage signal. The low voltage swing pad driver and receiver generates a relatively low voltage swing when compared to CMOS full-scale voltage swings thereby significantly reducing the possibility of introducing any noise and/or distortion of data that is communicated via the interface.

Abstract: An operational amplifier includes a first stage with a first differential transistor pair inputting a differential input signal at their gates, a first tail current source transistor connected to sources of the first differential transistor pair, and a load transistor pair connected in series with the drain of first differential transistor pair. An input stage includes a second differential transistor pair connected to respective drains of the first differential transistor pair at their gates, and a second tail current transistor connected to sources of the differential transistor pair. An output stage outputs a signal corresponding to the differential input signal.

Abstract: A circuit for clamping a TV signal includes an input capacitor coupled to the TV signal, an analog-to-digital converter that outputs a digital signal corresponding to TV signal, a comparator that compares the digital signal to a black level signal, and a high impedance driver that charges the input capacitor in response to an output of the comparator.

Abstract: A CMOSFET switch includes a NMOSFET, a PMOSFET, an input formed at the connection of the source terminals of the MOSFETs, and an output formed at the connection of the drain terminals of the MOSFETs. At least one of the MOSFETs is characterized by a small magnitude inherent threshold voltage, or the CMOSFET switch has at least one circuit that is capable of reducing a voltage difference between the source and body terminals of a MOSFET, or both. The variations in on resistance can be reduced over a wide common mode range by reducing the threshold voltages of the NMOSFET and the PMOSFET of the CMOSFET switch.

Abstract: An operational amplifier includes a first stage with a first differential transistor pair inputting a differential input signal at their gates, a first tail current source transistor connected to sources of the first differential transistor pair, and a load transistor pair connected in series with the drain of first differential transistor pair. An input stage includes a second differential transistor pair connected to respective drains of the first differential transistor pair at their gates, and a second tail current transistor connected to sources of the differential transistor pair. An output stage outputs a signal corresponding to the differential input signal.

Abstract: A method is described that involves directing a signal through a hysteresis comparator. Then, determining if an output signal of the hysteresis comparator, in response to the signal, is an AC signal or a DC signal. Then, deactivating a signal reception unit that receives the signal if the hysteresis comparator output signal corresponds to a DC signal; or, activating the signal reception unit if the hysteresis comparator output signal corresponds to an AC signal.

Abstract: Low voltage swing pad driver and receiver. A transmitter portion and a receiver portion are implemented within various devices that communicate using low voltage swing pads communicatively coupled via a trace. The transmitter portion of one device generates a current signal that is pushed/pulled to a low voltage swing pad and is then passed across the trace to another low voltage swing pad. The transmitter portion includes a current driver that outputs the current signal to the low voltage swing pads, and the receiver portion includes a trans-impedance amplifier that transforms the received current signal into a voltage signal. The low voltage swing pad driver and receiver generates a relatively low voltage swing when compared to CMOS full-scale voltage swings thereby significantly reducing the possibility of introducing any noise and/or distortion of data that is communicated via the interface.

Abstract: An input buffer amplifier has a symmetrical centroidal layout. The input buffer amplifier includes two half differential amplifiers that have substantially identical layouts. Each half amplifier receives the input signal in-parallel, and the outputs of the differential half amplifiers are wire-ored together. The input buffer amplifier is symmetrical about both horizontal and vertical lines of symmetry. Furthermore, FET devices forming the half amplifiers are interlaced to create the horizontal line of symmetry. The overall horizontal and vertical symmetry of the input buffer amplifier improves the device matching between differential signal paths. In other words, the devices in the half amplifiers that process the positive and negative components of the differential signal are more closely matched. This reduces differential offsets and common mode offsets that can occur when devices are not matched properly.

Abstract: A multi-path unity gain buffer circuit and method are implemented in a slew amplifier. The multi-path unity buffer has a high frequency signal path and a low frequency signal path. The high frequency signal path has a differential amplifier powered for providing a high frequency, low accuracy buffering operation. The low frequency signal path is coupled to the high frequency signal path. The low frequency signal path has an operational amplifier powered to provide a low frequency, high bandwidth buffering operation. An output of the operational amplifier is fed back to an input of the operational amplifier through a current varying element that varies current levels of the input of the operational amplifier to remove a level shift of an output signal of the differential amplifier.

Abstract: A method is described that involves directing a signal through a hysteresis comparator. Then, determining if an output signal of the hysteresis comparator, in response to the signal, is an AC signal or a DC signal. Then, deactivating a signal reception unit that receives the signal if the hysteresis comparator output signal corresponds to a DC signal; or, activating the signal reception unit if the hysteresis comparator output signal corresponds to an AC signal.

Abstract: An output driver (121) for a 10BaseT/100BaseTX transceiver provides a drive capability for either a 10BaseT output or a 100BaseTX output. The driver includes a voltage-to-current converter for converting the voltage to a current level which is then selectably switched to the input of two constant output impedance buffers (327) and (328). For the 100BaseTX mode, a constant current is provided to the buffers and then the current switched in a multi-level mode in accordance with an MLT-3 encoding scheme with a current switch (311). The buffers (327) and (328) are trimmed as a function of temperature by varying the current generated by the voltage-to-current converter (303). This trimming is facilitated by generating an internal current with the voltage-to-current converter (303) and then summing therewith a zero temperature coefficient current referenced to an external resistor.