Patents by Inventor Sumio Ikegawa

Sumio Ikegawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240420796
    Abstract: A memory device including a first configuration bit group including a plurality of bits, the plurality of bits including: a plurality of configuration bits; at least one redundant configuration bit; a plurality of configuration bit multiplexers each configured to receive (i) a first input from a first bit in the plurality of bits and/or a second input from a second bit in the plurality of bits and (ii) a third input from a decoder, each of the first, second, and third inputs indicating a respective logical state, wherein the logical state includes a first state or a second state; and wherein, based on the logical state of the third input received from the decoder, each configuration bit multiplexer is configured to output: the logical state of the first input from the first bit, or the logical state of the second input from the second bit.
    Type: Application
    Filed: June 11, 2024
    Publication date: December 19, 2024
    Applicant: Everspin Technologies, Inc.
    Inventors: Syed M. ALAM, Jacob T. WILLIAMS, Michael A. SADD, Kerry Joseph NAGEL, Sumio IKEGAWA, Frederick B. MANCOFF, Sanjeev AGGARWAL
  • Patent number: 12167702
    Abstract: The present disclosure is drawn to, among other things, a magnetoresistive device and a magnetoresistive memory comprising a plurality of such magnetoresistive devices. In some aspects, a magnetoresistive device may include a magnetically fixed region, a magnetically free region above or below the magnetically fixed region, and an intermediate region positioned between the magnetically fixed region and the magnetically free region, wherein the intermediate region includes a first dielectric material. The magnetoresistive device may also include encapsulation layers formed on opposing side walls of the magnetically free region, wherein the encapsulation layers include the first dielectric material.
    Type: Grant
    Filed: March 20, 2023
    Date of Patent: December 10, 2024
    Assignee: Everspin Technologies, Inc.
    Inventors: Sumio Ikegawa, Han Kyu Lee, Sanjeev Aggarwal, Jijun Sun, Syed M. Alam, Thomas Andre
  • Publication number: 20240315145
    Abstract: A magnetoresistive device comprises a fixed magnetic region positioned on or over a first electrically conductive region, an intermediate layer positioned on or over the fixed magnetic region, a free magnetic region positioned on or over the intermediate layer, and a metal insertion substance positioned in contact with the free magnetic region, wherein the metal insertion substance includes one or more transition metal elements.
    Type: Application
    Filed: May 24, 2024
    Publication date: September 19, 2024
    Applicant: Everspin Technologies, Inc.
    Inventor: Sumio IKEGAWA
  • Patent number: 12029137
    Abstract: A magnetoresistive device comprises a fixed magnetic region positioned on or over a first electrically conductive region, an intermediate layer positioned on or over the fixed magnetic region, a free magnetic region positioned on or over the intermediate layer, and a metal insertion substance positioned in contact with the free magnetic region, wherein the metal insertion substance includes one or more transition metal elements.
    Type: Grant
    Filed: November 8, 2021
    Date of Patent: July 2, 2024
    Assignee: Everspin Technologies, Inc.
    Inventor: Sumio Ikegawa
  • Publication number: 20240006011
    Abstract: The present disclosure is drawn to, among other things, a method of managing a memory device. In some aspects, the method includes determining whether a first address for a page in a first memory region is mapped in a map table, setting a target address as a second address identified in the map table as being mapped to the first address, setting the target address as the first address, determining a number of bits that fail in each word of a plurality of first-layer error correction code (ECC) words for the target address, and adding the target address to the map table, writing-back contents from the target address to a repair address in the first memory region, and updating the map table by mapping the target address to the repair address.
    Type: Application
    Filed: September 15, 2023
    Publication date: January 4, 2024
    Applicant: Everspin Technologies, Inc.
    Inventors: Syed M. ALAM, Jason JANESKY, Han Kyu LEE, Hamid ALMASI, Pedro SANCHEZ, Cristian P. MASGRAS, Iftekhar RAHMAN, Sumio IKEGAWA, Sanjeev AGGARWAL, Dimitri HOUSSAMEDDINE, Frederick Charles NEUMEYER
  • Patent number: 11798646
    Abstract: The present disclosure is drawn to, among other things, a method of managing a memory device. In some aspects, the method includes determining whether a first address for a page in a first memory region is mapped in a map table, setting a target address as a second address identified in the map table as being mapped to the first address, setting the target address as the first address, determining a number of bits that fail in each word of a plurality of first-layer error correction code (ECC) words for the target address, and adding the target address to the map table, writing-back contents from the target address to a repair address in the first memory region, and updating the map table by mapping the target address to the repair address.
    Type: Grant
    Filed: October 27, 2021
    Date of Patent: October 24, 2023
    Assignee: Everspin Technologies, Inc.
    Inventors: Syed M. Alam, Jason Janesky, Han Kyu Lee, Hamid Almasi, Pedro Sanchez, Cristian P. Masgras, Iftekhar Rahman, Sumio Ikegawa, Sanjeev Aggarwal, Dimitri Houssameddine, Frederick Charles Neumeyer
  • Publication number: 20230309416
    Abstract: The present disclosure is drawn to, among other things, a magnetoresistive device and a magnetoresistive memory comprising a plurality of such magnetoresistive devices. In some aspects, a magnetoresistive device may include a magnetically fixed region, a magnetically free region above or below the magnetically fixed region, and an intermediate region positioned between the magnetically fixed region and the magnetically free region, wherein the intermediate region includes a first dielectric material. The magnetoresistive device may also include encapsulation layers formed on opposing side walls of the magnetically free region, wherein the encapsulation layers include the first dielectric material.
    Type: Application
    Filed: March 20, 2023
    Publication date: September 28, 2023
    Applicant: Everspin Technologies, Inc.
    Inventors: Sumio IKEGAWA, Han Kyu Lee, Sanjeev AGGARWAL, Jijun SUN, Syed M. ALAM, Tom ANDRE
  • Publication number: 20230263071
    Abstract: A magnetoresistive stack may include a first electrically conductive material, a fixed region having a fixed magnetic state, a free region configured to have a first magnetic state and a second magnetic state, a dielectric layer disposed between the fixed region and the free region, a spacer region, and a cap layer disposed between the spacer region and the free region. The free region may include a layer of ferromagnetic material, an insertion layer, an iPMA layer, and/or a low saturation magnetization layer.
    Type: Application
    Filed: February 11, 2022
    Publication date: August 17, 2023
    Applicant: Everspin Technologies, Inc.
    Inventors: Sumio IKEGAWA, Jijun SUN, Monika ARORA
  • Patent number: 11637235
    Abstract: The present disclosure is drawn to, among other things, a magnetoresistive device and a magnetoresistive memory comprising a plurality of such magnetoresistive devices. In some aspects, a magnetoresistive device may include a magnetically fixed region, a magnetically free region above or below the magnetically fixed region, and an intermediate region positioned between the magnetically fixed region and the magnetically free region, wherein the intermediate region includes a first dielectric material. The magnetoresistive device may also include encapsulation layers formed on opposing side walls of the magnetically free region, wherein the encapsulation layers include the first dielectric material.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: April 25, 2023
    Assignee: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Sumio Ikegawa, Han Kyu Lee, Sanjeev Aggarwal, Jijun Sun, Syed M. Alam, Thomas Andre
  • Patent number: 11488647
    Abstract: Aspects of the present disclosure are directed to magnetic tunnel junction (MTJ) structures comprising multiple MTJ bits connected in series. For example, a magnetic tunnel junction (MTJ) stack according to the present disclosure may include at least a first MTJ bit and a second MTJ bit stacked above the first MTJ bit, and a resistance state of the MTJ stack may be read by passing a single read current through both the first MTJ bit and the second MTJ bit.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: November 1, 2022
    Assignee: Everspin Technologies, Inc.
    Inventors: Jijun Sun, Frederick Mancoff, Jason Janesky, Kevin Conley, Lu Hui, Sumio Ikegawa
  • Publication number: 20220139488
    Abstract: The present disclosure is drawn to, among other things, a method of managing a memory device. In some aspects, the method includes determining whether a first address for a page in a first memory region is mapped in a map table, setting a target address as a second address identified in the map table as being mapped to the first address, setting the target address as the first address, determining a number of bits that fail in each word of a plurality of first-layer error correction code (ECC) words for the target address, and adding the target address to the map table, writing-back contents from the target address to a repair address in the first memory region, and updating the map table by mapping the target address to the repair address.
    Type: Application
    Filed: October 27, 2021
    Publication date: May 5, 2022
    Applicant: Everspin Technologies, Inc.
    Inventors: Syed M. ALAM, Jason JANESKY, Han Kyu LEE, Hamid ALMASI, Pedro SANCHEZ, Cristian P. MASGRAS, Iftekhar RAHMAN, Sumio IKEGAWA, Sanjeev AGGARWAL, Dimitri HOUSSAMEDDINE, Frederick Charles NEUMEYER
  • Patent number: 11264564
    Abstract: A magnetoresistive device may include one or more electrodes or electrically conductive lines and a fixed region and a free region disposed between the electrodes or electrically conductive lines. The fixed region may have a fixed magnetic state and the free region may be configured to have a first magnetic state and a second magnetic state. The free region may store a first value when in the first magnetic state and store a second value when in the second magnetic state. The magnetoresistive device may further include a dielectric layer between the free region and the fixed region and a spin-Hall (SH) material proximate to at least a portion of the free region. An insertion layer may be disposed between the SH material and the free region.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: March 1, 2022
    Assignee: Everspin Technologies, Inc.
    Inventors: Sumio Ikegawa, Hamid Almasi, Shimon, Kerry Nagel, Han Kyu Lee
  • Publication number: 20220059755
    Abstract: A magnetoresistive device comprises a fixed magnetic region positioned on or over a first electrically conductive region, an intermediate layer positioned on or over the fixed magnetic region, a free magnetic region positioned on or over the intermediate layer, and a metal insertion substance positioned in contact with the free magnetic region, wherein the metal insertion substance includes one or more transition metal elements.
    Type: Application
    Filed: November 8, 2021
    Publication date: February 24, 2022
    Applicant: Everspin Technologies, Inc.
    Inventor: Sumio IKEGAWA
  • Publication number: 20210375342
    Abstract: Aspects of the present disclosure are directed to magnetic tunnel junction (MTJ) structures comprising multiple MTJ bits connected in series. For example, a magnetic tunnel junction (MTJ) stack according to the present disclosure may include at least a first MTJ bit and a second MTJ bit stacked above the first MTJ bit, and a resistance state of the MTJ stack may be read by passing a single read current through both the first MTJ bit and the second MTJ bit.
    Type: Application
    Filed: June 27, 2019
    Publication date: December 2, 2021
    Applicant: Everspin Technologies, Inc.
    Inventors: Jijun SUN, Frederick MANCOFF, Jason JANESKY, Kevin CONLEY, Lu HUI, Sumio IKEGAWA
  • Patent number: 11189781
    Abstract: A magnetoresistive device comprises a fixed magnetic region positioned on or over a first electrically conductive region, an intermediate layer positioned on or over the fixed magnetic region, a free magnetic region positioned on or over the intermediate layer, and a metal insertion substance positioned in contact with the free magnetic region, wherein the metal insertion substance includes one or more transition metal elements.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: November 30, 2021
    Assignee: Everspin Technologies, Inc.
    Inventor: Sumio Ikegawa
  • Patent number: 11127896
    Abstract: The present disclosure is drawn to, among other things, a magnetoresistive memory. The magnetoresistive memory comprises a plurality of magnetoresistive memory devices, wherein each magnetoresistive memory device includes a fixed magnetic region, a free magnetic region, and an intermediate region disposed in between the fixed and free magnetic regions. The magnetoresistive memory further comprises a first conductor extending adjacent each magnetoresistive memory device of the plurality of magnetoresistive devices, wherein the first conductor is in electrical contact with the free magnetic region of each magnetoresistive memory device.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: September 21, 2021
    Assignee: Everspin Technologies, Inc.
    Inventors: Syed M. Alam, Thomas Andre, Frederick Mancoff, Sumio Ikegawa
  • Publication number: 20210288245
    Abstract: A magnetoresistive device includes a magnetically fixed region and a magnetically free region positioned on opposite sides of a tunnel barrier region. One or more transition regions, including at least a first transition region and second transition region, is positioned between the magnetically fixed region and the tunnel barrier region. The first transition region includes a non-ferromagnetic transition metal and the second transition region includes an alloy including iron and boron.
    Type: Application
    Filed: July 29, 2019
    Publication date: September 16, 2021
    Applicant: Everspin Technologies, Inc.
    Inventors: Renu WHIG, Sumio IKEGAWA, Jon SLAUGHTER, Michael TRAN, Jacob Wang CHENCHEN, Ganesh Kolliyil RAJAN
  • Publication number: 20210249589
    Abstract: A magnetoresistive device may include one or more electrodes or electrically conductive lines and a fixed region and a free region disposed between the electrodes or electrically conductive lines. The fixed region may have a fixed magnetic state and the free region may be configured to have a first magnetic state and a second magnetic state. The free region may store a first value when in the first magnetic state and store a second value when in the second magnetic state. The magnetoresistive device may further include a dielectric layer between the free region and the fixed region and a spin-Hall (SH) material proximate to at least a portion of the free region. An insertion layer may be disposed between the SH material and the free region.
    Type: Application
    Filed: February 6, 2020
    Publication date: August 12, 2021
    Applicant: Everspin Technologies, Inc.
    Inventors: Sumio IKEGAWA, Hamid ALMASI, SHIMON, Kerry NAGEL, Han Kyu LEE
  • Patent number: 10825500
    Abstract: A magnetoresistive memory device that stores data in the synthetic antiferromagnet (SAF) included in each spin-torque memory cell provides for more robust data storage. In normal operation, the memory cells use the free portion of the memory cell for data storage. Techniques for storing data in the reference portions of memory cells are presented, where an unbalanced SAF that includes ferromagnetic layers having different magnetic moments is used to lower the switching barrier for the SAF and allow for writing data values to the SAF using lower currents and magnetic fields than would be required for a balanced SAF.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: November 3, 2020
    Assignee: Everspin Technologies, Inc.
    Inventors: Han-Jong Chia, Sumio Ikegawa, Michael Tran, Jon Slaughter
  • Publication number: 20200235288
    Abstract: The present disclosure is drawn to, among other things, a magnetoresistive device and a magnetoresistive memory comprising a plurality of such magnetoresistive devices. In some aspects, a magnetoresistive device may include a magnetically fixed region, a magnetically free region above or below the magnetically fixed region, and an intermediate region positioned between the magnetically fixed region and the magnetically free region, wherein the intermediate region includes a first dielectric material. The magnetoresistive device may also include encapsulation layers formed on opposing side walls of the magnetically free region, wherein the encapsulation layers include the first dielectric material.
    Type: Application
    Filed: January 16, 2020
    Publication date: July 23, 2020
    Applicant: Everspin Technologies, Inc.
    Inventors: Sumio IKEGAWA, Han Kyu LEE, Sanjeev AGGARWAL, Jijun SUN, Syed M. ALAM, Thomas ANDRE