Patents by Inventor Sumio Ikegawa

Sumio Ikegawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190131519
    Abstract: A magnetoresistive stack includes a seed region formed above a base region, a fixed magnetic region formed above the seed region and an intermediate region positioned between the fixed magnetic region and a free magnetic region. The base region may be formed of a material having a lower standard free energy of oxidation than iron.
    Type: Application
    Filed: November 2, 2018
    Publication date: May 2, 2019
    Applicant: Everspin Technologies, Inc.
    Inventors: Sumio Ikegawa, Jon Slaughter, Renu Whig
  • Patent number: 10255961
    Abstract: A magnetoresistive memory device that stores data in the synthetic antiferromagnet (SAF) included in each spin-torque memory cell provides for more robust data storage. In normal operation, the memory cells use the free portion of the memory cell for data storage. Techniques for storing data in the reference portions of memory cells are presented, where an unbalanced SAF that includes ferromagnetic layers having different magnetic moments is used to lower the switching barrier for the SAF and allow for writing data values to the SAF using lower currents and magnetic fields than would be required for a balanced SAF.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: April 9, 2019
    Assignee: Everspin Technologies, Inc.
    Inventors: Han-Jong Chia, Sumio Ikegawa, Michael Tran, Jon Slaughter
  • Publication number: 20190013460
    Abstract: A magnetoresistive device comprises a fixed magnetic region positioned on or over a first electrically conductive region, an intermediate layer positioned on or over the fixed magnetic region, a free magnetic region positioned on or over the intermediate layer, and a metal insertion substance positioned in contact with the free magnetic region, wherein the metal insertion substance includes one or more transition metal elements.
    Type: Application
    Filed: July 9, 2018
    Publication date: January 10, 2019
    Applicant: Everspin Technologies, Inc.
    Inventor: Sumio IKEGAWA
  • Publication number: 20180205396
    Abstract: Techniques for recovering preprogrammed data from non-volatile memory are provided that include majority voting and/or use of one or more levels of ECC correction. Embodiments include storage of multiple copies of the data where ECC correction is performed before and after majority voting with respect to the multiple copies. Multiple levels of ECC correction can also be performed where one level of ECC is performed at the local level (e.g. on-chip), whereas another level of ECC correction is performed at a system level.
    Type: Application
    Filed: December 19, 2017
    Publication date: July 19, 2018
    Applicant: Everspin Technologies Inc.
    Inventors: Sumio Ikegawa, Jon Slaughter
  • Publication number: 20180182443
    Abstract: A magnetoresistive memory device that stores data in the synthetic antiferromagnet (SAF) included in each spin-torque memory cell provides for more robust data storage. In normal operation, the memory cells use the free portion of the memory cell for data storage. Techniques for storing data in the reference portions of memory cells are presented, where an unbalanced SAF that includes ferromagnetic layers having different magnetic moments is used to lower the switching barrier for the SAF and allow for writing data values to the SAF using lower currents and magnetic fields than would be required for a balanced SAF.
    Type: Application
    Filed: December 22, 2017
    Publication date: June 28, 2018
    Applicant: Everspin Technologies, Inc.
    Inventors: Han-Jong Chia, Sumio Ikegawa, Michael Tran, Jon Slaughter
  • Patent number: 9678179
    Abstract: According to one embodiment, a tester includes a magnetic shield portion having a space which is shielded from an external magnetic field, a controller generating a test signal for testing a magnetic memory having a magnetoresistive element provided in the space, an interface portion in the space, the interface portion which functions as an interface between the controller and the magnetic memory, and a magnetic field generating portion in the space, the magnetic field generating portion generating a test magnetic field while the magnetic memory is tested by the test signal.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: June 13, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsuya Kishi, Sumio Ikegawa
  • Publication number: 20160055891
    Abstract: According to one embodiment, a magnetic memory includes a memory cell array including magnetoresistive elements, a heater and a temperature sensor provided in the memory cell array, a heater driver which drives the heater, a temperature detector which detects a first temperature sensed by the temperature sensor, and a control circuit which controls the heater driver based on the first temperature.
    Type: Application
    Filed: January 9, 2015
    Publication date: February 25, 2016
    Inventors: Hisanori AIKAWA, Masayoshi IWAYAMA, Akiyuki MURAYAMA, Tatsuya KISHI, Sumio IKEGAWA
  • Patent number: 9269889
    Abstract: According to one embodiment, a semiconductor memory device comprises a memory cell array. The memory cell array has a plurality of magnetic tunnel junction (MTJ) elements. Each of the MTJ elements has a first magnetic layer, a second magnetic layer and a non-magnetic layer therebetween, and a hard mask layer is arranged above the second magnetic layer. The plurality of MTJ elements have a first MTJ element having a first hard mask layer and a second MTJ element having a second hard mask layer, and a dimension of, the first hard mask layer is greater than that of the second hard mask layer.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: February 23, 2016
    Inventors: Keiji Hosotani, Sumio Ikegawa, Tatsuya Kishi
  • Patent number: 9203015
    Abstract: According to one embodiment, a magnetic storage device includes an insulating region, a lower electrode including a first portion formed in a hole provided in the insulating region and a second portion protruded from the insulating region, a spacer insulating film formed on a side surface of at least the second portion of the lower electrode, a magnetic tunneling junction portion formed on a top surface of the lower electrode, and an upper electrode formed on the magnetic tunneling junction portion.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: December 1, 2015
    Inventors: Hisanori Aikawa, Masayoshi Iwayama, Akiyuki Murayama, Sumio Ikegawa
  • Publication number: 20150263264
    Abstract: According to one embodiment, a semiconductor memory device comprises a memory cell array. The memory cell array has a plurality of magnetic tunnel junction (MTJ) elements. Each of the MTJ elements has a first magnetic layer, a second magnetic layer and a non-magnetic layer therebetween, and a hard mask layer is arranged above the second magnetic layer. The plurality of MTJ elements have a first MTJ element having a first hard mask layer and a second MTJ element having a second hard mask layer, and a dimension of, the first hard mask layer is greater than that of the second hard mask layer.
    Type: Application
    Filed: September 5, 2014
    Publication date: September 17, 2015
    Inventors: Keiji HOSOTANI, Sumio IKEGAWA, Tatsuya KISHI
  • Publication number: 20150260804
    Abstract: According to one embodiment, a tester includes a magnetic shield portion having a space which is shielded from an external magnetic field, a controller generating a test signal for testing a magnetic memory having a magnetoresistive element provided in the space, an interface portion in the space, the interface portion which functions as an interface between the controller and the magnetic memory, and a magnetic field generating portion in the space, the magnetic field generating portion generating a test magnetic field while the magnetic memory is tested by the test signal.
    Type: Application
    Filed: September 5, 2014
    Publication date: September 17, 2015
    Inventors: Tatsuya KISHI, Sumio IKEGAWA
  • Patent number: 8878321
    Abstract: According to one embodiment, a magnetoresistive element comprises a first magnetic layer, in which a magnetization direction is variable and is perpendicular to a film surface, a tunnel barrier layer that is formed on the first magnetic layer, and a second magnetic layer that is formed on the tunnel barrier layer, a magnetization direction of the second magnetic layer being variable and being perpendicular to the film surface. The second magnetic layer comprises a body layer that constitutes an origin of perpendicular magnetic anisotropy, and an interface layer that is formed between the body layer and the tunnel barrier layer. The interface layer has a permeability higher than that of the body layer and a planar size larger than that of the body layer.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: November 4, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisanori Aikawa, Hiroaki Yoda, Masahiko Nakayama, Tatsuya Kishi, Sumio Ikegawa
  • Publication number: 20140284743
    Abstract: According to one embodiment, a magnetic storage device includes an insulating region, a lower electrode including a first portion formed in a hole provided in the insulating region and a second portion protruded from the insulating region, a spacer insulating film formed on a side surface of at least the second portion of the lower electrode, a magnetic tunneling junction portion formed on a top surface of the lower electrode, and an upper electrode formed on the magnetic tunneling junction portion.
    Type: Application
    Filed: August 30, 2013
    Publication date: September 25, 2014
    Inventors: Hisanori AIKAWA, Masayoshi IWAYAMA, Akiyuki MURAYAMA, Sumio IKEGAWA
  • Patent number: 8634238
    Abstract: According to one embodiment, a magnetic memory element includes a memory layer, a first nonmagnetic layer, a reference layer, a second nonmagnetic layer, and an adjustment layer which are stacked. The adjustment layer is configured to reduce a leakage magnetic field from the reference layer. The adjustment layer is formed by stacking an interface layer provided on the second nonmagnetic layer, and a magnetic layer having magnetic anisotropy perpendicular to a film surface. Saturation magnetization of the interface layer is larger than that of the magnetic layer.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: January 21, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiko Nakayama, Hisanori Aikawa, Masaru Toko, Hiroaki Yoda, Tatsuya Kishi, Sumio Ikegawa
  • Patent number: 8530987
    Abstract: A magnetic memory includes a magnetoresistive element. The magnetoresistive element includes a reference layer having an invariable magnetization direction, a storage layer having a variable magnetization direction, and a spacer layer provided between the reference layer and the storage layer. The storage layer has a multilayered structure including first and second magnetic layers, the second magnetic layer is provided between the first magnetic layer and the spacer layer and has a magnetic anisotropy energy lower than that of the first magnetic layer, and an exchange coupling constant Jex between the first magnetic layer and the second magnetic layer is not more than 5 erg/cm2.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: September 10, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisanori Aikawa, Tadashi Kai, Masahiko Nakayama, Sumio Ikegawa, Naoharu Shimomura, Eiji Kitagawa, Tatsuya Kishi, Jyunichi Ozeki, Hiroaki Yoda, Satoshi Yanagi
  • Patent number: 8472242
    Abstract: A magnetoresistive effect memory of an aspect of the present invention including a magnetoresistive effect element including a first magnetic layer having an invariable magnetization direction, a second magnetic layer having a variable magnetization direction, and an interlayer provided between the first magnetic layer and the second magnetic layer, and a reading circuit which passes a pulse-shaped read current through the magnetoresistive effect element to read data stored in the magnetoresistive effect element, wherein the pulse width of the read current is shorter than a period from an initial state to a cooperative coherent precession movement of magnetizations included in the second magnetic layer.
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: June 25, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoharu Shimomura, Eiji Kitagawa, Sumio Ikegawa, Yoshihisa Iwata
  • Publication number: 20130099337
    Abstract: According to one embodiment, a magnetic memory element includes a memory layer, a first nonmagnetic layer, a reference layer, a second nonmagnetic layer, and an adjustment layer which are stacked. The adjustment layer is configured to reduce a leakage magnetic field from the reference layer. The adjustment layer is formed by stacking an interface layer provided on the second nonmagnetic layer, and a magnetic layer having magnetic anisotropy perpendicular to a film surface. Saturation magnetization of the interface layer is larger than that of the magnetic layer.
    Type: Application
    Filed: September 5, 2012
    Publication date: April 25, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masahiko Nakayama, Hisanori Aikawa, Masaru Toko, Hiroaki Yoda, Tatsuya Kishi, Sumio Ikegawa
  • Publication number: 20130069184
    Abstract: According to one embodiment, a magnetoresistive element comprises a first magnetic layer, in which a magnetization direction is variable and is perpendicular to a film surface, a tunnel barrier layer that is formed on the first magnetic layer, and a second magnetic layer that is formed on the tunnel barrier layer, a magnetization direction of the second magnetic layer being variable and being perpendicular to the film surface. The second magnetic layer comprises a body layer that constitutes an origin of perpendicular magnetic anisotropy, and an interface layer that is formed between the body layer and the tunnel barrier layer. The interface layer has a permeability higher than that of the body layer and a planar size larger than that of the body layer.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 21, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hisanori AIKAWA, Hiroaki YODA, Masahiko NAKAYAMA, Tatsuya KISHI, Sumio IKEGAWA
  • Patent number: 8378437
    Abstract: A magnetoresistive effect element includes a reference layer, a recording layer, and a nonmagnetic layer. The reference layer is made of a magnetic material, has an invariable magnetization which is perpendicular to a film surface. The recording layer is made of a magnetic material, has a variable magnetization which is perpendicular to the film surface. The nonmagnetic layer is arranged between the reference layer and the recording layer. A critical diameter which is determined by magnetic anisotropy, saturation magnetization, and switched connection of the recording layer and has a single-domain state as a unique stable state or a critical diameter which has a single-domain state as a unique stable state and is inverted while keeping the single-domain state in an inverting process is larger than an element diameter of the magnetoresistive effect element.
    Type: Grant
    Filed: October 9, 2008
    Date of Patent: February 19, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiko Nakayama, Kay Yakushiji, Sumio Ikegawa, Shinji Yuasa, Tadashi Kai, Toshihiko Nagase, Minoru Amano, Hisanori Aikawa, Tatsuya Kishi, Hiroaki Yoda
  • Patent number: 8349622
    Abstract: A magneto-resistive element according to an aspect of the present invention includes a free layer whose magnetized state changes and a pinned layer whose magnetized state is fixed. The free layer comprises first and second ferromagnetic layers and a non-magnetic layer which is arranged between the first and second ferromagnetic layers. An intensity of exchange coupling between the first and second ferromagnetic layers is set so that an astroid curve in a hard axis direction opens.
    Type: Grant
    Filed: January 29, 2009
    Date of Patent: January 8, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Sumio Ikegawa, Masahiko Nakayama, Tadashi Kai, Eiji Kitagawa, Hiroaki Yoda