Abstract: A driving circuit according to an embodiment of the present invention includes an input terminal, unit circuits connected to the input terminal, and output terminals electrically connected to the input terminals. Each of the unit circuits is enabled in response to a control signal inputted via the input terminal.

Abstract: A display apparatus and a multi-display apparatus having larger display areas. The display apparatus includes a first insulating substrate, as well as a plurality of gate lines and a plurality of data lines on the first insulating substrate, where the plurality of gate lines is arranged to intersect the plurality of data lines. A plurality of storage electrode lines is arranged substantially parallel to the plurality of gate lines. A gate drive chip is mounted off of the first insulating substrate and electrically connected to the plurality of gate lines and the plurality of storage electrode lines. The gate drive chip is configured to apply a gate voltage to the gate lines and a storage voltage to the storage electrode lines.

Abstract: The present invention discloses a data driving method, the method including receiving data corresponding to a plurality of pixels. Received data are converted into data voltages of an analog type to be output to a plurality of data lines. One of a first data voltage and a last data voltage of the data voltages is output to a dummy data line adjacent to the data lines.

Abstract: A gate drive portion for a display device including multiple pixels having first and second sub-pixels includes a first shift register generating a first output signal in response to a first gate clock signal, a second shift register generating a second output signal in response to a second gate clock signal, a level shifter coupled to the first and second shift registers and amplifying the first and second output signals, and an output buffer coupled to the level shifter and generating first and second gate signals. The first gate signal is generated in synchronization with the first gate clock signal and the second gate signal is generated in synchronization with the second gate clock signal. Accordingly, the charging time of the first and second sub-pixels may be improved by separately driving the odd-numbered and even-numbered sub-pixels and the visibility of the LCD device may also be improved.

Abstract: A display device includes gate lines; data lines; charge control lines each including a charge control voltage input pad; first and second thin film transistors (TFTs) each including control and input electrodes connected to the gate and data lines, respectively; a first liquid crystal capacitor connected to an output electrode of the first TFT; a second liquid crystal capacitor connected to an output electrode of the second TFT; a charge control TFT including a control electrode and an input electrode connected to one of the charge control lines and the second pixel electrode, respectively; and a charge-down capacitor connected to an output electrode of the charge control TFT. A duration time of a turn-on voltage pulse applied to the charge control TFT is different from a duration time of a turn-on voltage pulse applied to the first TFT transistor or the second TFT.

Abstract: A display device includes a first unit pixel disposed in a first pixel column and a first pixel row, and a second unit pixel disposed in the first pixel column and a second pixel row adjacent to the first pixel row, and first and second gate lines extending in a row direction and having gate voltage input pads at a terminal portion thereof. First and second data lines extend in a column direction and are connected to the first unit pixel and the second unit pixel, respectively. A first charge control line extends in the row direction and has a charge control gate voltage input pad disposed at a terminal portion thereof. The first gate line is connected to the first unit pixel and the second gate line is connected to the second unit pixel. The first gate line and the second gate line simultaneously receive a same gate pulse.

Abstract: A power circuit for a liquid crystal display includes a voltage divider which generates a voltage-divided voltage between a first power source and a second power source, an operational amplifier which receives the voltage-divided voltage to output a driving voltage, a first switch connected between the first power source and a common node, and a second switch connected between the second power source and the common node. The first switch provides a first current path between the first power source and the common node in response to the driving voltage, and the second switch provides a second current path between the second power source and the common node in response to the driving voltage.

Abstract: A gate drive portion for a display device including multiple pixels having first and second sub-pixels includes a first shift register generating a first output signal in response to a first gate clock signal, a second shift register generating a second output signal in response to a second gate clock signal, a level shifter coupled to the first and second shift registers and amplifying the first and second output signals, and an output buffer coupled to the level shifter and generating first and second gate signals. The first gate signal is generated in synchronization with the first gate clock signal and the second gate signal is generated in synchronization with the second gate clock signal. Accordingly, the charging time of the first and second sub-pixels may be improved by separately driving the odd-numbered and even-numbered sub-pixels and the visibility of the LCD device may also be improved.

Abstract: In accordance with one or more embodiments of the present disclosure, a touch screen display device includes a touch screen display panel, a first integrated circuit (IC) chip, and a second IC chip. The touch screen display panel includes a plurality of gate lines, a plurality of data lines, a plurality of pixels, a plurality of first sensing lines, a plurality of second sensing lines, and a plurality of touch sensors. The first IC chip includes a gate driver which transmits a plurality of gate signals to the gate lines, respectively, and a first read-out unit which receives respective output signals of the first sensing lines. The second IC chip includes a data driver which applies a plurality of image data voltages to the data lines, respectively, and a second read-out unit which receives respective output signals of the second sensing lines.

Abstract: A liquid crystal display device having improved visibility is disclosed. The liquid crystal display, in accordance with an embodiment, includes a liquid crystal panel including a plurality of display blocks, each display block including a plurality of gate lines, a plurality of data lines, and a plurality of pixels coupled to the corresponding gate lines and data lines; a timing controller providing an integration signal including data and a charge share control signal; and a plurality of data-driving chips corresponding to the plurality of display blocks, each of the data-driving chips being coupled to the timing controller in a point-to-point relation, receiving the integration signal, and short-circuiting the plurality of data lines in the corresponding display blocks with one another during charge-share periods, wherein at least two of the plurality of data-driving chips adjust the charge-share periods to be different from each other.

Abstract: Provided are a division-type DAC, a method for driving the division-type DAC, a source driver and a display device having the division-type DAC. A decoder of the DAC is divided into a plurality of decoders, so that the number of transistors of each decoder is reduced and the size of the decoder is reduced. Therefore, the DAC with the reduced size, the method for driving the DAC, the source driver and the display device having the DAC with the reduced size can be provided.

Abstract: A signal transfer film includes a base film, a lead line formed on the base film and a passivation layer protecting the lead line. The passivation layer includes a nonlinear edge portion formed at a boundary region between the lead line and the passivation layer. The nonlinear edge portion of the passivation layer disperses a stress concentrated to the boundary region in various directions when the base film is bent. Thus, the signal transfer film may prevent breaking of the lead line, thereby enhancing yield thereof.

Abstract: In a display apparatus, a display panel includes touch sensors that make contact with a common electrode by an external pressure to output a common voltage, and a sensing driver receives the common voltage from the touch sensors to generate a sensing signal. A controller receives the sensing signal from the sensing driver and calculates position information to which the external pressure is applied based on the sensing signal. The sensing driver includes a switching circuit that receives a switching signal from the controller to switch the common voltage. Thus, the display apparatus prevents the common voltage from being input during a period where a voltage level of the common voltage is abnormally high, thereby preventing a logic circuit of the sensing driver from being damaged.

Abstract: A driving chip and a display apparatus having the same. The driving chip includes a plurality of driving circuits which generate a driving signal, a plurality of output pads which output the driving signals to external signal lines, a plurality of connection lines which connect the plurality of driving circuits and the plurality of output pads, respectively, wherein at least one of the plurality of connection lines includes a resistance-control unit which controls resistance values of the connection lines to be the same, and reduces a resistance deviation between the connection lines. Thus, resistances of connection lines are controlled to be substantially the same, or resistance deviation is reduced by adjusting the resistances of the respective connection lines of an output port. Accordingly, a signal delay or a signal distortion induced by the resistance deviation of the connection lines in the driving chip is prevented, and defective images are removed.

Abstract: A liquid crystal display having data driving apparatus comprising first and second output switches, a charge sharing line, and first and second charge sharing switches. The first output switch switches an electrical connection between a first amplifier providing a positive gradation voltage and a first data line in response to a control signal. The second output switch switches an electrical connection between a second amplifier providing a negative gradation voltage and a second data line in response to the control signal. The first charge sharing switch switches an electrical connection between the first data line and the charge sharing line in response to the control signal. The second charge sharing switch switches an electrical connection between the second data line and the charge sharing line in response to the control signal.

Abstract: A display device and a method for driving the same wherein the timing of the gate clock signal, which is an output of a timing controller, is changed to a time before a data latch signal is applied, so that degradation of the image due to gate noise can be prevented. That is, a gate turn-on voltage is applied before the data latch signal to turn on thin film transistors in an interval in which a gate turn-off voltage is stabilized. Accordingly, the generation of horizontal streaks in the lower portion of the display device is prevented.

Abstract: A signal transfer member for a liquid crystal display (LCD) apparatus includes a power line for receiving power from an external source and for driving a semiconductor chip disposed on the transfer member or the display apparatus. The power line is bent so as to incorporate a serpentine structure, which enables the length of the power line to be easily adjusted and results in the line being longer than a power line formed with a relatively straight structure. Accordingly, the length of the power line can be adjusted to take into account the respective impedances of the chip and the external source so as to suppress electromagnetic waves in the power line. This prevents the creation of noise, distortion of signals, damage to the semiconductor chip, and disconnection of the input interconnection thereof that are caused by the electromagnetic waves, so that product yields are thereby improved.

Abstract: A chip film package which can achieve a fine pitch and a display panel assembly having the same are provided. The chip film package includes a base film made of an insulating material, a wire pattern formed on the base film to form a predetermined circuit, and a lead which is formed at one end of the wire pattern to be electrically connected to an external terminal, wherein a width (Wb) of the bottom surface of the lead adjacent to the base film is smaller than a width (Wt) of the top surface of the lead connected to the external terminal.

Abstract: A signal generating circuit for a liquid crystal display (LCD) includes circuitry adapted to receive a gate clock signal and an output enable signal. The gate clock signal is a combination of a gate-on signal and a gate-off signal and the output enable signal is operable to adjust the width of the gate-on signal. The signal generating circuit adjusts the output enable signal such that a falling edge of the output enable signal overlaps a rising edge of the gate clock signal and thereby delays the gate clock signal for a selected amount of time.

Abstract: A liquid crystal display is provided, which includes: a liquid crystal panel including a plurality of pixels including switching elements, a plurality of gate lines for transmitting gate signals to the switching elements, and a plurality of data lines for transmitting data voltages to the pixels; a data driver including a plurality of data driving ICs connected to respective sets of the data lines, receiving image data, and applying the data voltages corresponding to the image data to the data lines; and a gate driver applying the gate voltages to the gate lines, wherein the data driving ICs are supplied with a ground voltage and a supply voltage and voltage levels of the image data swing with reference to a reference voltage lower than the supply voltage.