Abstract: A chip type electronic component for test is provided with an element body, and four or more terminal electrodes placed on the exterior of the element body. The element body has a plurality of laminated insulator layers, and a plurality of internal electrodes arranged to be opposed to each other with the insulator layer in between. Each of the internal electrodes is connected to at least one same terminal electrode out of the four or more terminal electrodes and connected to any one terminal electrode except for the at least one same terminal electrode.

Abstract: A chip type electronic component for test is provided with an element body, and four or more terminal electrodes placed on the exterior of the element body. The element body has a plurality of laminated insulator layers, and a plurality of internal electrodes arranged to be opposed to each other with the insulator layer in between. Each of the internal electrodes is connected to at least one same terminal electrode out of the four or more terminal electrodes and connected to any one terminal electrode except for the at least one same terminal electrode.

Abstract: Internal electrodes A1 to D1 and A2 to D2 are laid in layers at spaces in the direction of thickness of a ceramic body 1. Lead electrodes a1 to d1 and a2 to d2 are led out to a side face to form lead portions. Dummy electrodes 51 to 58 have one-side ends led out to a side face to form lead portions in layers provided with the internal electrodes A1 to D1 and A2 to D2. The lead portion of a lead electrode a1 to d1 or a2 to d2 of each layer is superposed over the lead portion of a dummy electrode 51 to 58 belonging to another layer in the direction of thickness.

Abstract: Internal electrodes A1 to D1 and A2 to D2 are laid in layers at spaces in the direction of thickness of a ceramic body 1. Lead electrodes a1 to d1 and a2 to d2 are led out to a side face to form lead portions. Dummy electrodes 51 to 58 have one-side ends led out to a side face to form lead portions in layers provided with the internal electrodes A1 to D1 and A2 to D2. The lead portion of a lead electrode a1 to d1 or a2 to d2 of each layer is superposed over the lead portion of a dummy electrode 51 to 58 belonging to another layer in the direction of thickness.

Abstract: A multiterminal multilayer ceramic electronic device comprising a capacitor body formed by stacking dielectric layers, a plurality of internal electrodes separated by dielectric layers inside the capacitor body, each having at least one lead led out toward any side face of the capacitor body, and differing in position of arrangement of the lead with the nearby internal electrodes, and a plurality of terminal electrodes arranged at the outside surface of the capacitor body and connected to any of the plurality of internal electrodes through the leads. Between the internal electrodes not formed a lead and the terminal electrodes are formed a compensation layers. The compensation layers have approximately the same thickness as that of the internal electrodes, being not connected to at least one of the internal electrodes and the terminal electrodes, and separated from each other on an identical plane.

Abstract: The multilayer electronic device comprises a dielectric body formed by stacking dielectric layers. Flat first internal electrodes and flat second internal electrodes insulated via dielectric layers and arranged facing to the first internal electrodes are alternately stacked. First through-hole electrodes are connected to the first internal electrodes by penetrating, penetrate the second internal electrodes without connecting thereto and extend crossing the internal electrodes. The second through-hole electrodes are connected to the second internal electrodes by penetrating, penetrate the first internal electrodes without connecting thereto and extend crossing the internal electrodes. The first terminal electrodes are arranged on the outer surface of the dielectric body and connected to the first through-hole electrodes.

Abstract: The multilayer electronic device comprises a dielectric body formed by stacking dielectric layers. Flat first internal electrodes and flat second internal electrodes insulated via dielectric layers and arranged facing to the first internal electrodes are alternately stacked. First through-hole electrodes are connected to the first internal electrodes by penetrating, penetrate the second internal electrodes without connecting thereto and extend crossing the internal electrodes. The second through-hole electrodes are connected to the second internal electrodes by penetrating, penetrate the first internal electrodes without connecting thereto and extend crossing the internal electrodes. The first terminal electrodes are arranged on the outer surface of the dielectric body and connected to the first through-hole electrodes.

Abstract: The invention provides an electronic device comprising a first metal layer containing a first metal converted into an oxide upon firing in an oxidizing atmosphere and a second metal layer formed by firing of a second metal particle containing a metal that is not oxidized upon firing in an oxidizing atmosphere, with an intermediate oxide layer interleaved between these two metal layers. The intermediate oxide layer contains an oxide of the first metal contained in the first metal layer. Preferably, the second metal particle contained in the second metal layer is dispersed in the intermediate oxide layer. A uniform oxide layer is obtained at a simple step, and the resistance value provided by the oxide layer is easily controllable with high precision. It is thus possible to achieve an electronic device in which the bonding strength of the oxide layer with respect to the other metal-containing layer is improved with an improvement in the bonding strength with respect to lead wires.