Abstract: Aspects of the disclosure provide for an antenna system. The antenna system includes a main reflector, a phased array feed, and a mechanical steering system. The phased array feed is configured to receive and/or transmit signals reflected off the main reflector and to electronically steer a transmitted signal on a first axis. The main reflector and the phased array feed are both attached to the mechanical steering system, and the mechanical steering system is configured to move the transmitted signal along a second axis.

Abstract: A wireless communication system. The system comprises transmitter circuitry (BST1), the transmitter circuitry comprising encoder circuitry (50) for transmitting a plurality of frames (FR). Each of the plurality of frames comprises a primary synchronization code (PCS) and a second synchronization code (SSC). The encoder circuitry comprises of circuitry (501) for providing the primary synchronization code in response to a first sequence (32). The encoder circuitry further comprises circuitry (502) for providing the secondary synchronization code in response to a second sequence (54) and a third sequence (56). The second sequence is selected from a plurality of sequences. Each of the plurality of sequences is orthogonal with respect to all other sequences. The third sequence is a subset of bits from the first sequence.

Abstract: A wireless communication system. The system comprises transmitter circuitry (BST1), the transmitter circuitry comprising encoder circuitry (50) for transmitting a plurality of frames (FR). Each of the plurality of frames comprises a primary synchronization code (PCS) and a second synchronization code (SSC). The encoder circuitry comprises of circuitry (501) for providing the primary synchronization code in response to a first sequence (32). The encoder circuitry further comprises circuitry (502) for providing the secondary synchronization code in response to a second sequence (54) and a third sequence (56). The second sequence is selected from a plurality of sequences. Each of the plurality of sequences is orthogonal with respect to all other sequences. The third sequence is a subset of bits from the first sequence.

Abstract: A wireless communication system. The system comprises transmitter circuitry (BST1), the transmitter circuitry comprising encoder circuitry (50) for transmitting a plurality of frames (FR). Each of the plurality of frames comprises a primary synchronization code (PCS) and a second synchronization code (SSC). The encoder circuitry comprises of circuitry (501) for providing the primary synchronization code in response to a first sequence (32). The encoder circuitry further comprises circuitry (502) for providing the secondary synchronization code in response to a second sequence (54) and a third sequence (56). The second sequence is selected from a plurality of sequences. Each of the plurality of sequences is orthogonal with respect to all other sequences. The third sequence is a subset of bits from the first sequence.

Abstract: A wireless communication system. The system comprises transmitter circuitry (BST1), the transmitter circuitry comprising encoder circuitry (50) for transmitting a plurality of frames (FR). Each of the plurality of frames comprises a primary synchronization code (PCS) and a second synchronization code (SSC). The encoder circuitry comprises of circuitry (501) for providing the primary synchronization code in response to a first sequence (32). The encoder circuitry further comprises circuitry (502) for providing the secondary synchronization code in response to a second sequence (54) and a third sequence (56). The second sequence is selected from a plurality of sequences. Each of the plurality of sequences is orthogonal with respect to all other sequences. The third sequence is a subset of bits from the first sequence.

Abstract: A wireless communication system. The system comprises transmitter circuitry (BST1), the transmitter circuitry comprising encoder circuitry (50) for transmitting a plurality of frames (FR). Each of the plurality of frames comprises a primary synchronization code (PCS) and a second synchronization code (SSC). The encoder circuitry comprises of circuitry (501) for providing the primary synchronization code in response to a first sequence (32). The encoder circuitry further comprises circuitry (502) for providing the secondary synchronization code in response to a second sequence (54) and a third sequence (56). The second sequence is selected from a plurality of sequences. Each of the plurality of sequences is orthogonal with respect to all other sequences. The third sequence is a subset of bits from the first sequence.

Abstract: A wireless communication system. The system comprises transmitter circuitry (BST1), the transmitter circuitry comprising encoder circuitry (50) for transmitting a plurality of frames (FR). Each of the plurality of frames comprises a primary synchronization code (PCS) and a secondary synchronization code (SSC). The encoder circuitry comprises of circuitry (501) for providing the primary synchronization code in response to a first sequence (32). The encoder circuitry further comprises circuitry (502) for providing the secondary synchronization code in response to a second sequence (54) and a third sequence (56). The second sequence is selected from a plurality of sequences. Each of the plurality of sequences is orthogonal with respect to all other sequences in the plurality of sequences. The third sequence comprises a subset of bits from the first sequence.

Abstract: A circuit for detecting a serial signal comprises a first circuit coupled to receive the serial signal during a predetermined plurality of time periods of substantially equal duration. The first circuit is coupled to receive a first code. The first circuit is arranged to compare a part of the serial signal corresponding to each time period of the plurality of timer periods to the first code, thereby producing a match signal. The first circuit accumulates the match signal from each of the each time period of the plurality of time periods.

Abstract: A method of processing data comprises the receiving a frame of data having a predetermined number of time slots (502,504,506). Each time slot comprises a respective plurality of data symbols (520). The method further comprises a primary (508), a secondary (510) and a tertiary (512) synchronization code in each said predetermined number of time slots.

Abstract: A wireless communication system. The system comprises transmitter circuitry (BST1), the transmitter circuitry comprising encoder circuitry (50) for transmitting a plurality of frames (FR). Each of the plurality of frames comprises a primary synchronization code (PCS) and a secondary synchronization code (SSC). The encoder circuitry comprises of circuitry (501) for providing the primary synchronization code in response to a first sequence (32). The encoder circuitry further comprises circuitry (502) for providing the secondary synchronization code in response to a second sequence (54) and a third sequence (56). The second sequence is selected from a plurality of sequences. Each of the plurality of sequences is orthogonal with respect to all other sequences in the plurality of sequences. The third sequence comprises a subset of bits from the first sequence.

Abstract: A method of processing data comprises the receiving a frame of data having a predetermined number of time slots (502,504,506). Each time slot comprises a respective plurality of data symbols (520). The method further comprises a primary (508), a secondary (510) and a tertiary (512) synchronization code in each said predetermined number of time slots.

Abstract: A method of processing data comprises the receiving a frame of data having a predetermined number of time slots (502,504,506). Each time slot comprises a respective plurality of data symbols (520). The method further comprises a primary (508), a secondary (510) and a tertiary (512) synchronization code in each said predetermined number of time slots.

Abstract: A wireless communication system. The system comprises transmitter circuitry (BST1), the transmitter circuitry comprising encoder circuitry (50) for transmitting a plurality of frames (FR). Each of the plurality of frames comprises a primary synchronization code (PCS) and a secondary synchronization code (SSC). The encoder circuitry comprises of circuitry (501) for providing the primary synchronization code in response to a first sequence (32). The encoder circuitry further comprises circuitry (502) for providing the secondary synchronization code in response to a second sequence (54) and a third sequence (56). The second sequence is selected from a plurality of sequences. Each of the plurality of sequences is orthogonal with respect to all other sequences in the plurality of sequences. The third sequence comprises a subset of bits from the first sequence.

Abstract: A method of processing data comprises the receiving a frame of data having a predetermined number of time slots (502,504,506). Each time slot comprises a respective plurality of data symbols (520). The method further comprises a primary (508), a secondary (510) and a tertiary (512) synchronization code in each said predetermined number of time slots.

Abstract: A wireless communication system. The system comprises transmitter circuitry (BST1), the transmitter circuitry comprising encoder circuitry (50) for transmitting a plurality of frames (FR). Each of the plurality of frames comprises a primary synchronization code (PCS) and a secondary synchronization code (SSC). The encoder circuitry comprises of circuitry (501) for providing the primary synchronization code in response to a first sequence (32). The encoder circuitry further comprises circuitry (502) for providing the secondary synchronization code in response to a second sequence (54) and a third sequence (56). The second sequence is selected from a plurality of sequences. Each of the plurality of sequences is orthogonal with respect to all other sequences in the plurality of sequences. The third sequence comprises a subset of bits from the first sequence.

Abstract: A method of processing data comprises the receiving a frame of data having a predetermined number of time slots (502,504,506). Each time slot comprises a respective plurality of data symbols (520). The method further comprises a primary (508), a secondary (510) and a tertiary (512) synchronization code in each said predetermined number of time slots.

Abstract: A wireless communication system. The system comprises transmitter circuitry (BST1), the transmitter circuitry comprising encoder circuitry (50) for transmitting a plurality of frames (FR). Each of the plurality of frames comprises a primary synchronization code (PCS) and a secondary synchronization code (SSC). The encoder circuitry comprises of circuitry (501) for providing the primary synchronization code in response to a first sequence (32). The encoder circuitry further comprises circuitry (502) for providing the secondary synchronization code in response to a second sequence (54) and a third sequence (56). The second sequence is selected from a plurality of sequences. Each of the plurality of sequences is orthogonal with respect to all other sequences in the plurality of sequences. The third sequence comprises a subset of bits from the first sequence.

Abstract: A method of processing data comprises the receiving a frame of data having a predetermined number of time slots (502,504,506). Each time slot comprises a respective plurality of data symbols (520). The method further comprises a primary (508), a secondary (510) and a tertiary (512) synchronization code in each said predetermined number of time slots.

Abstract: A system operable for ranging synchronization is provided. The system includes a first component that is operable to analyze a set of signals. The first component is operable to determine a subset of the set of signals based on a condition, at least some of the set of signals including ranging codes. The system also includes a second component that is operable to receive the subset of the set of signals and to determine a preferred candidate of ranging codes.

Abstract: The invention solves the problem of efficiently generating pseudo noise sequences with an arbitrary offset delay. Novel and improved architectures are used, based on the matrix-vector pseudo noise generators. A first embodiment of this invention includes a plurality of serially connected transition matrix multiplication circuits producing a plurality of output state matrices. A second embodiment of this invention combines a first stage having plurality of matrix multiplication circuits connected to a first multiplexer circuit which selects an state matrix or one of the matrix products with a serial chain of matrix generator circuits including second matrix multiplication circuit and a second multiplexer selecting either a first input or the output of the second matrix multiplication circuit.