Abstract: This invention provide parallel interference cancellation for wireless communication base stations. Received user inputs symbols are spread by means of pseudo-noise sequences to form user input chip vectors. These are added together and interpreted to form chip vectors of interference samples. These chip vectores are despread to form interference output symbols by pseudo-noise sequences. The interference output signals are subtracted from the received user input symbols to obtain a first estimate of transmitted symbols. This process may be continued for two or more iterations to obtain better interference cancellation.

Abstract: A wireless communication system (10). The system comprises a transceiver (20), and the transceiver comprises a code counter (LCSTC 22c) and a clock oscillator (26) for advancing a count in the code counter. The transceiver further comprises circuitry (30) for receiving a time message based on a system time external from the transceiver and circuitry (28) for determining a system time count and for storing the system time count to the code counter in response to the time message. Further, code counter continues to be advanced from the system time count in response to the clock oscillator. The transceiver further comprises circuitry (28) for repeatedly evaluating the count in the code counter, after advancement from the system time count, to ascertain whether the count has drifted to an inaccurate count. Lastly, the transceiver further comprises circuitry (28), responsive to detecting an inaccurate count, for adjusting the inaccurate count to a perceived accurate count.

Abstract: A system operable for ranging synchronization is provided. The system includes a first component that is operable to analyze a set of signals. The first component is operable to determine a subset of the set of signals based on a condition, at least some of the set of signals including ranging codes. The system also includes a second component that is operable to receive the subset of the set of signals and to determine a preferred candidate of ranging codes.

Abstract: A wireless communication system. The system comprises transmitter circuitry (BST1), the transmitter circuitry comprising encoder circuitry (50) for transmitting a plurality of frames (FR). Each of the plurality of frames comprises a primary synchronization code (PCS) and a secondary synchronization code (SSC). The encoder circuitry comprises of circuitry (501) for providing the primary synchronization code in response to a first sequence (32). The encoder circuitry further comprises circuitry (502) for providing the secondary synchronization code in response to a second sequence (54) and a third sequence (56). The second sequence is selected from a plurality of sequences. Each of the plurality of sequences is orthogonal with respect to all other sequences in the plurality of sequences. The third sequence comprises a subset of bits from the first sequence.

Abstract: A wireless communication system. The system comprises transmitter circuitry (BST1), the transmitter circuitry comprising encoder circuitry (50) for transmitting a plurality of frames (FR). Each of the plurality of frames comprises a primary synchronization code (PCS) and a secondary synchronization code (SSC). The encoder circuitry comprises of circuitry (501) for providing the primary synchronization code in response to a first sequence (32). The encoder circuitry further comprises circuitry (502) for providing the secondary synchronization code in response to a second sequence (54) and a third sequence (56). The second sequence is selected from a plurality of sequences. Each of the plurality of sequences is orthogonal with respect to all other sequences in the plurality of sequences. The third sequence comprises a subset of bits from the first sequence.

Abstract: A circuit for processing binary sequences is designed with a plurality of stages (530–534) coupled to provide plural signal paths (526,528). Each stage includes respective signal paths (550,562) for a first Ra1(k) and a second Rb1(k) data sequence. Each stage further includes a respective delay circuit (502) having a different delay from said respective delay circuit of each other stage (504,506) of the plurality of stages. A stage having a greatest delay (502) precedes other stages (504,506) in the plurality of stages of at least one of the plural signal paths.

Abstract: A wireless base station (20). The base station comprises at least one receive antenna (ATRXn) for receiving communication signals from at least one transmitting station (UST), and the signals are spread with a plurality of chips. The base station further comprises circuitry (52) for selecting a set of chips corresponding to a first signal received by the at least one receive antenna and circuitry (60) for forming a set of de-spread chips corresponding to the set of chips and in response to a code. Still further, the base station comprises a functional data path (56) comprising an accumulator for receiving the set of de-spread chips and circuitry for receiving an instruction. The functional data path is operable in response to a first instruction, received by the circuitry for receiving an instruction, to accumulate (621 or 622) a first number of de-spread chips in the set of de-spread chips for producing at least one corresponding symbol.

Abstract: A method (70) of operating a wireless receiver (UST). The method receives a wireless communicated signal, wherein the signal comprises a first synchronization channel component. The method also correlates a synchronization channel value (PSC) to the signal to produce a plurality of correlation samples in response to a correlation between the synchronization channel value and the signal. Further, the method compares (72) the plurality of correlation samples to a threshold (?) and stores as a first set of correlation samples selected ones of the plurality of correlation samples that exceed the threshold and are within a first time sample period, wherein each of the correlation samples in the first set has a corresponding sample time relative to the first time sample period. Finally, the method combines (74) a second set of correlation samples with the first set of correlation samples.

Abstract: A circuit for detecting a serial signal comprises a first circuit (400) coupled to receive the serial signal (200) during a predetermined plurality of time periods of substantially equal duration. The first circuit is coupled to receive a first code (414). The first circuit is arranged to compare a part of the serial signal corresponding to each time period of the plurality of time periods to the first code, thereby producing a match signal. The first circuit accumulates the match signal from each of the each time period of the plurality of time periods.

Abstract: A method (70) of operating a wireless receiver (UST). The method receives a wireless communicated signal, wherein the signal comprises asymmetrically spaced synchronization channel components. The method also defines (72) a set of signals from the communicated signal, wherein the set spans a number of equal duration time slots and comprises at least a first synchronization channel component and a second synchronization channel component. The method also forms (76) a first signal combination by combining a first portion of the set of signals with a second portion of the set of signals, and it forms (78) a second signal combination by combining a third portion of the set of signals with a fourth portion of the set of signals. Finally, the method detects (80, 82, 84) a location of the first synchronization channel component and a location of the second synchronization channel component in response to at least one of the first and second signal combinations.

Abstract: A mechanism for implementing time tracking and early/ontime/late correlation processing in a vector correlator has been implemented to accommodate processing of data when the earliest chips in a triple data input buffer are to be processed and time tracking needs to be done to an earlier sample and further to accommodate processing of data when chips being processed are the last chips in a circular input buffer and time tracking needs to be done to a later sample.

Abstract: A circuit for detecting a serial signal comprises a first circuit (400) coupled to receive the serial signal (200) during a predetermined plurality of time periods of substantially equal duration. The first circuit is coupled to receive a first code (414). The first circuit is arranged to compare a part of the serial signal corresponding to each time period of the plurality of time periods to the first code, thereby producing a match signal. The first circuit accumulates the match signal from each of the each time period of the plurality of time periods.

Abstract: A frequency bin method of carrier frequency acquisition uses a plurality of predetermined carrier frequency offset bins. A single bin is selected from among the plurality of bins. A local VCO is then adjusted to remove the carrier frequency offset associated with the single selected bin. Carrier frequency acquisition is then attempted using the adjusted VCO. If successful, the receiver enters its steady state operating mode. If unsuccessful, a new bin is selected and the VCO is again adjusted using the new carrier frequency offset associated with the newly selected bin. The process is repeated until successful communication is achieved in association with a properly adjusted VCO.

Abstract: A system and method for maintaining timing in a CDMA rake receiver has a global chip counter that counts CDMA signal chips as they arrive at the CDMA rake receiver. A local pseudo-noise (PN) sequence replica of the incoming CDMA signal is generated and used to perform a sliding window correlation of the locally generated PN sequence replica with the incoming signal to correlate the CDMA signal timing relative to stored CDMA signal chip counts. The PN sequence timing is maintained relative to GCC, which avoids having to keep track of absolute time within each Rake finger.

Abstract: The present application discloses an improved mobile communications architecture, in which each base station broadcasts not only data which has been spread by that station's long code word, but also (intermittently) code identification data which has not been spread. The code identification data is a block code which includes multiple symbols, so that multiple intermittent transmissions are required to complete the transmission of the code identification data. This transmission lets the mobile station shorten the search for the base station's long code word in two ways: the code identification data gives at least some information about the long code itself; and the phase of the block code gives at least some information about the phase of the long code word.

Abstract: A method of processing data comprises the receiving a frame of data having a predetermined number of time slots (502,504,506). Each time slot comprises a respective plurality of data symbols (520). The method further comprises a primary (508), a secondary (510) and a tertiary (512) synchronization code in each said predetermined number of time slots.

Abstract: A method of processing data comprises the receiving a frame of data having a predetermined number of time slots (502,504,506). Each time slot comprises a respective plurality of data symbols (520). The method further comprises a primary (508), a secondary (510) and a tertiary (512) synchronization code in each said predetermined number of time slots.

Abstract: The invention solves the problem of efficiently generating pseudo noise sequences with an arbitrary offset delay. Novel and improved architectures are used, based on the matrix-vector pseudo noise generators.

Abstract: A wireless communication system (10). The system comprises a transceiver (20), and the transceiver comprises a code counter (LCSTC 22c) and a clock oscillator (26) for advancing a count in the code counter. The transceiver further comprises circuitry (30) for receiving a time message based on a system time external from the transceiver and circuitry (28) for determining a system time count and for storing the system time count to the code counter in response to the time message. Further, code counter continues to be advanced from the system time count in response to the clock oscillator. The transceiver further comprises circuitry (28) for repeatedly evaluating the count in the code counter, after advancement from the system time count, to ascertain whether the count has drifted to an inaccurate count. Lastly, the transceiver further comprises circuitry (28), responsive to detecting an inaccurate count, for adjusting the inaccurate count to a perceived accurate count.

Abstract: A method of processing data comprises the receiving a frame of data having a predetermined number of time slots (502,504,506). Each time slot comprises a respective plurality of data symbols (520). The method further comprises a primary (508), a secondary (510) and a tertiary (512) synchronization code in each said predetermined number of time slots.