Abstract: A programmable, flexible, vector correlation engine for CDMA mobile and base station chip rate signal processing. A correlator co-processor (CCP) performs the de-spreading tasks for a RAKE receiver, early/late correlations for time tracking, and has provision for coherent accumulation of different lengths. The CCP also performs energy estimation and non-coherent accumulation functions. The CCP can also perform correlation functions required for delay profile estimation, and for search/acquisition functions. The same centralized Data Path is used to perform all these functions; a common controller generates signals into the Data Path in response to tasks initiated by a host processor (e.g., DSP). The tasks written into the CCP are performed effectively in parallel by the CCP Data Path.

Abstract: A wireless base station (20). The base station comprises at least one receive antenna (ATRXn) for receiving communication signals from at least one transmitting station (UST), and the signals are spread with a plurality of chips. The base station further comprises circuitry (52) for selecting a set of chips corresponding to a first signal received by the at least one receive antenna and circuitry (60) for forming a set of de-spread chips corresponding to the set of chips and in response to a code. Still further, the base station comprises a functional data path (56) comprising an accumulator for receiving the set of de-spread chips and circuitry for receiving an instruction. The functional data path is operable in response to a first instruction, received by the circuitry for receiving an instruction, to accumulate (621 or 622) a first number of de-spread chips in the set of de-spread chips for producing at least one corresponding symbol.

Abstract: A circuit is designed with a plurality of logic circuits (370-374) for producing an offset state matrix. The circuit includes a first logic circuit (380-383) coupled to receive N elements of a respective row of a transition matrix and N elements of column of an input state matrix. The first logic circuit produces a multi-bit logical combination of corresponding bits of the respective row and the column. A second logic circuit (390) is coupled to receive the multi-bit logical combination and produces a respective element of the offset state matrix.

Abstract: This invention provide parallel interference cancellation for wireless communication base stations. Received user inputs symbols are spread by means of pseudo-noise sequences to form user input chip vectors. These are added together and interpreted to form chip vectors of interference samples. These chip vectores are despread to form interference output symbols by means of said pseudo-noise sequences. The interference output signals are subtracted from the received user input symbols to obtain a first estimate of transmitted symbols. This process may be continued for two or more iterations to obtain better interference cancellation.

Abstract: A WCDMA system and method of data communication allows a receiver to reliably achieve carrier frequency acquisition following turn-on without use of temperature compensation. Initial frequency acquisition is achieved by estimating the signal path position having the largest magnitude and then by estimating the phase difference associated with primary synchronization channels at a predetermined position within a single frame. The estimated phase difference is used to estimate a carrier frequency offset that can be used to adjust the local voltage controlled oscillator frequency, thereby acquiring the WCDMA communication signal carrier frequency.

Abstract: Pseudo-noise code modulated QPSK signals are correlated with a rotated version of the conjugate pseudo-noise code to lessen computational complexity. The rotation emulates a phase shift in the transmission channel, and the rotation is removed without computation by channel estimation.

Abstract: A mechanism for implementing time tracking and early/ontime/late correlation processing in a vector correlator has been implemented to accommodate processing of data when the earliest chips in a triple data input buffer are to be processed and time tracking needs to be done to an earlier sample and further to accommodate processing of data when chips being processed are the last chips in a circular input buffer and time tracking needs to be done to a later sample.

Abstract: A circuit is designed with a plurality of logic circuits (370-374) for producing an offset state matrix. The circuit includes a first logic circuit (380-383) coupled to receive N elements of a respective row of a transition matrix and N elements of column of an input state matrix. The first logic circuit produces a multi-bit logical combination of corresponding bits of the respective row and the column. A second logic circuit (390) is coupled to receive the multi-bit logical combination and produces a respective element of the offset state matrix.

Abstract: The present invention is a digital transmissions receiver system which includes digital transmissions receiver (10) and correlation co-processor (12). Optionally, an additional memory device (14) for storing input and output buffers may also be included. Communications between the digital transmissions receiver (10), the correlator co-processor (12), and the optional memory device (14) are carried out over co-processor interface (16). The correlation co-processor (12) performs correlation operations at the request of the digital transmissions receiver (10). Power consumption in the correlation co-processor (12) is reduced by performing the requested correlation operations in stages. The number of stages used is inversely proportional to the number of gates required to implement the correlation function. Thus, the more stages used, the fewer gates required. This, in turn, provides lower power consumption as compared with a non-staged implementation of the correlation function.

Abstract: A circuit for detecting a signal is designed with a first serial circuit coupled to receive an input signal in response to a clock signal. The first serial circuit (121) has N taps (142-146) arranged to produce a respective plurality of first tap signals from the input signal (111). A first logic circuit (130, 132, 134, 148) is coupled to receive the plurality of first tap signals and one of N predetermined signals and the complement of N predetermined signals. The first logic circuit produces a first output signal (150) in response to the clock signal, the plurality of first tap signals and the one of N predetermined signals and the complement of N predetermined signals. A second serial circuit coupled to receive the first output signal. The second serial circuit has M taps (150, 172-184) arranged to produce a respective plurality of second tap signals from the first output signal, wherein a ratio of N/M is no greater than four.

Abstract: A communication system (10) comprising circuitry (RCVR1) for receiving a bitstream packet (P). The bitstream packet comprises at least three groups of bits: (i) a plurality of preamble prefix bits having a predetermined bit pattern; (ii) a plurality of synchronization word bits following the plurality of preamble prefix bits; and (iii) a plurality of data bits following the plurality of synchronization word bits. The system further includes circuitry for completing a carrier and clock recovery operation in response to receiving a first portion of the plurality of preamble prefix bits. Still further, the system includes circuitry (30) for determining a location of the plurality of synchronization word bits within the bitstream packet. The circuitry for determining comprises circuitry (36) for performing a number of comparisons between a bit test pattern vector (32) and a sample vector (34) of bits from the bitstream packet.

Abstract: A circuit is designed with a plurality of logic circuits (370-374) for producing an offset state matrix. The circuit includes a first logic circuit (380-383) coupled to receive N elements of a respective row of a transition matrix and N elements of column of an input state matrix. The first logic circuit produces a multi-bit logical combination of corresponding bits of the respective row and the column. A second logic circuit (390) is coupled to receive the multi-bit logical combination and produces a respective element of the offset state matrix.

Abstract: The present application discloses an improved mobile communications architecture, in which each base station broadcasts not only data which has been spread by that station's long code word, but also (intermittently) code identification data which has not been spread. The code identification data is a block code which includes multiple symbols, so that multiple intermittent transmissions are required to complete the transmission of the code identification data. This transmission lets the mobile station shorten the search for the base station's long code word in two ways: the code identification data gives at least some information about the long code itself; and the phase of the block code gives at least some information about the phase of the long code word.