Abstract: A semiconductor device including a channel region of stacked semiconductor layers arranged in at least one cluster, wherein each cluster includes a pair of the semiconductor sheets with a dielectric material present therebetween. The semiconductor device further includes a gate structure encapsulating the channel region of stacked semiconductor sheets arranged in clusters. Source and drain regions are present on opposing sides of the channel region.

Abstract: A semiconductor device includes a first transistor, a second transistor and a third transistor provided on a substrate, the first to third transistors respectively including source and drain regions spaced apart from each other, a gate structure extending in a first direction on the substrate and interposed between the source and drain regions, and a channel region connecting the source and drain regions to each other. A channel region of the second transistor and a channel region of the third transistor respectively include a plurality of channel portions, the plurality of channel portions spaced apart from each other in a second direction, perpendicular to an upper surface of the substrate, and connected to the source and drain regions, respectively. A width of a channel portion of the third transistor in the first direction is greater than a width of a channel portion of the second transistor in the first direction.

Abstract: A method is presented for forming a vertical transport field effect transistor (VTFET). The method includes forming a plurality of fins over a substrate, depositing a sacrificial material adjacent the plurality of fins, forming self-aligned spacers adjacent the plurality of fins, removing the sacrificial material to define openings under the self-aligned spacers, filling the openings with bottom spacers, depositing an interlayer dielectric (ILD) after patterning, laterally etching the substrate such that bottom surfaces of the plurality of fins are exposed, the lateral etching defining cavities within the substrate, and filling the cavities with an epitaxial material such that epitaxial regions are defined each having a symmetric tapered shape under a twin-fin structure. The single fin device can be formed through additional patterning and bottom epi under the single fin device that has an asymmetric tapered shape.

Abstract: A semiconductor device fabrication method is provided. The semiconductor device fabrication method includes frontside semiconductor device processing on a frontside of a wafer, flipping the wafer, backside semiconductor device processing on a backside of the wafer and backside and frontside contact formation processing on the backside and frontside of the wafer, respectively.

Abstract: A semiconductor device fabrication method is provided. The semiconductor device fabrication method includes frontside semiconductor device processing on a frontside of a wafer, flipping the wafer, backside semiconductor device processing on a backside of the wafer and backside and frontside contact formation processing on the backside and frontside of the wafer, respectively.

Abstract: A MOSFET includes a semiconductor substrate, which has a body and an upper layer. The upper layer is doped differently than the body. The body and the upper layer are of a same crystal structure and orientation. The MOSFET also includes a p-type FET on the upper layer of the substrate. The p-type FET includes p-doped source/drain structures that sandwich one or more channels and a p gate stack with a p-type work function metal. In one or more embodiments, the p-doped source/drain structures are of the same crystal structure and orientation as the upper layer of the substrate and directly contact the upper layer of the substrate. In one or more embodiments, the upper layer of the substrate is doped differently than the p-doped source/drain structures, such that the p-doped source/drain structures and the upper layer of the substrate form pn-type diodes.

Abstract: A semiconductor device includes a FinFET fin. The same FinFET fin is associated with a bottom FinFET and a top FinFET. The FinFET fin includes a lower channel portion, associated with the bottom FinFET, a top channel portion, associated with the top FinFET, and a channel isolator between the bottom channel portion and the top channel portion. A lower gate includes a vertical portion that is upon a sidewall of the bottom channel portion. An isolation layer may be formed upon the lower gate if it is desired for the top FinFET fin and the bottom FinFET fin to not share a gate. An upper gate is upon the top channel portion and is further upon the isolation layer, if present, or is upon the lower gate.

Abstract: A semiconductor device includes an insulating layer on a substrate, a channel region on the insulating layer, a gate structure on the insulating layer, the gate structure crossing the channel region, source/drain regions on the insulating layer, the source/drain regions being spaced apart from each other with the gate structure interposed therebetween, the channel region connecting the source/drain regions to each other, and contact plugs connected to the source/drain regions, respectively. The channel region includes a plurality of semiconductor patterns that are vertically spaced apart from each other on the insulating layer, the insulating layer includes first recess regions that are adjacent to the source/drain regions, respectively, and the contact plugs include lower portions provided into the first recess regions, respectively.

Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate; a transistor stack structure formed on the semiconductor substrate, the transistor stack structure including a first FET and a second FET, where the first FET is a different polarity than the second FET; a first source-drain epitaxial layer of the first FET formed directly on the substrate adjacent to the first FET; and a second source-drain epitaxial layer of the second FET formed on the substrate adjacent to the second FET, wherein a bottom dielectric isolation layer is formed between the substrate and the second epitaxial layer.

Abstract: Stacked field effect transistors are provided such having a first power rail; a second power rail; a first Field Effect Transistor (FET) having a first gate connected to the first power rail; a second FET having a second gate connected to the second power rail; and an insulator separating the first FET from the second FET, wherein the first power rail, the second power rail, the first FET, and the second FET are aligned on a shared axis, and wherein the first power rail and the second power rail are located on opposite sides of the device.

Abstract: Double gate/gate-all-around and variable threshold voltage MOSFET devices and techniques for fabrication thereof in a single backside process are provided. In one aspect, a MOSFET device includes: a channel in between source/drain regions; at least one first gate disposed on a first side of the channel at a frontside of the MOSFET device; gate spacers offsetting the source/drain regions from the at least one first gate; and at least one second gate disposed on a second side of the channel directly opposite the at least one first gate at a backside of the MOSFET device. At least one gate contact can be present in direct contact with the at least one first gate and the at least one second gate. A method of forming a MOSFET device is also provided.

Abstract: A semiconductor device fabrication method is provided. The semiconductor device fabrication method includes frontside semiconductor device processing on a frontside of a wafer, flipping the wafer, backside semiconductor device processing on a backside of the wafer and backside and frontside contact formation processing on the backside and frontside of the wafer, respectively.

Abstract: Semiconductor channel layers vertically aligned and stacked one on top of another, each separated by a gate stack material, a source-drain epitaxy region adjacent to the semiconductor channel layers, a vertical side surface of the source-drain epitaxy region is adjacent to a vertical side surface of a conductive trench contact. A first set and a second set of semiconductor channel layers, a conductive trench contact between them and a source-drain between the first set and the conductive trench contact. Forming a first stack, a second stack and a third stack of nanosheet layers, forming a first, second and third sacrificial gate, forming a first source drain between the first and second stack, forming a second source drain between the second and third, forming a vertical trench in the first source drain while protecting the second source drain, and forming a stressor material layer in the vertical trench.

Abstract: A semiconductor device includes: a pair of wire patterns configured to extend in a first direction and formed on a substrate to be spaced apart from each other in a second direction, the pair of wire patterns disposed closest to each other in the second direction; a gate electrode configured to extend in the second direction on the substrate, the gate electrode configured to surround the wire patterns; and first isolation layers configured to extend in the first direction between the substrate and the gate electrode and formed to be spaced apart from each other in the second direction, the first isolation layers overlapping the pair of wire patterns in a third direction perpendicular to the first and second directions.

Abstract: A semiconductor device comprising at least one first gate all around channel having a horizontal physical orientation, wherein the at least one first gate all around channel is comprised of a first material, wherein the at least one first gate all around channel has a sidewall surface with (100) crystal orientation. At least one second gate all around channel having a vertical physical orientation, wherein the second channel is located above the at least one first gate all around channel, wherein the at least one second gate all around channel is comprised of a second material, wherein the at least one second gate all around channel has a sidewall surface with (110) crystal orientation. A gate metal enclosing the at least one first gate all around channel and the at least one second gate all around channel.

Abstract: A method for manufacturing a vertical transistor device includes forming a plurality of fins on a substrate, and forming a gate dielectric layer on the fins and on the substrate adjacent the fins. In the method, one or more sacrificial layers are formed on the gate dielectric layer, and portions of the gate dielectric layer and the one or more sacrificial layers are removed to define a plurality of gate regions. The method also includes depositing a dielectric fill layer in gaps left by the removed gate dielectric and sacrificial layers, and selectively removing the remaining portions of the one or more sacrificial layers to form a plurality of vacant areas in the gate regions. First and second gate structures are respectively formed in first and second vacant areas of the plurality of vacant areas. The first and second gate structures are recessed to a uniform height.

Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate; a transistor stack structure formed on the semiconductor substrate, the transistor stack structure including a first FET and a second FET, where the first FET is a different polarity than the second FET; a first source-drain epitaxial layer of the first FET formed directly on the substrate adjacent to the first FET; and a second source-drain epitaxial layer of the second FET formed on the substrate adjacent to the second FET, wherein a bottom dielectric isolation layer is formed between the substrate and the second epitaxial layer.

Abstract: A semiconductor device includes a first transistor, a second transistor and a third transistor provided on a substrate, the first to third transistors respectively including source and drain regions spaced apart from each other, a gate structure extending in a first direction on the substrate and interposed between the source and drain regions, and a channel region connecting the source and drain regions to each other. A channel region of the second transistor and a channel region of the third transistor respectively include a plurality of channel portions, the plurality of channel portions spaced apart from each other in a second direction, perpendicular to an upper surface of the substrate, and connected to the source and drain regions, respectively. A width of a channel portion of the third transistor in the first direction is greater than a width of a channel portion of the second transistor in the first direction.

Abstract: An embodiment of the invention may include a semiconductor structure and method of manufacturing. The semiconductor structure may include a top channel and a bottom channel, wherein the top channel includes a plurality of vertically oriented channels. The bottom channel includes a plurality of horizontally oriented channels. The semiconductor structure may include a gate surrounding the top channel and the bottom channel. The semiconductor structure may include spacers located on each side of the gate. A first spacer includes a dielectric material located between the plurality of vertically oriented channels. A second spacer includes a dielectric material located between the plurality of horizontally oriented channels. This may enable spacer formation between the vertical spacers.

Abstract: A semiconductor device includes a first transistor, a second transistor and a third transistor provided on a substrate, the first to third transistors respectively including source and drain regions spaced apart from each other, a gate structure extending in a first direction on the substrate and interposed between the source and drain regions, and a channel region connecting the source and drain regions to each other. A channel region of the second transistor and a channel region of the third transistor respectively include a plurality of channel portions, the plurality of channel portions spaced apart from each other in a second direction, perpendicular to an upper surface of the substrate, and connected to the source and drain regions, respectively. A width of a channel portion of the third transistor in the first direction is greater than a width of a channel portion of the second transistor in the first direction.