Patents by Inventor Sung-dae Suk

Sung-dae Suk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10734273
    Abstract: A semiconductor device includes: a pair of wire patterns configured to extend in a first direction and formed on a substrate to be spaced apart from each other in a second direction, the pair of wire patterns disposed closest to each other in the second direction; a gate electrode configured to extend in the second direction on the substrate, the gate electrode configured to surround the wire patterns; and first isolation layers configured to extend in the first direction between the substrate and the gate electrode and formed to be spaced apart from each other in the second direction, the first isolation layers overlapping the pair of wire patterns in a third direction perpendicular to the first and second directions.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: August 4, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung Dae Suk, Sang Hoon Lee, Masuoka Sadaaki, Han Su Oh
  • Patent number: 10453864
    Abstract: A semiconductor device includes a base substrate, a buried insulating film on the base substrate, a first semiconductor substrate pattern on the buried insulating film, a second semiconductor substrate pattern on the buried insulating film, the second semiconductor substrate pattern being spaced apart from the first semiconductor substrate pattern, a first device pattern on the first semiconductor substrate pattern, a second device pattern on the second semiconductor substrate pattern, the first and second device patterns having different characteristics from each other, an isolating trench between the first semiconductor substrate pattern and the second semiconductor substrate pattern, the isolating trench extending only partially into the buried insulating film, and a lower interlayer insulating film overlying the first device pattern and the second device pattern and filling the isolating trench.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: October 22, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung Dae Suk, Geum Jong Bae, Joo Hee Jeong
  • Patent number: 10403754
    Abstract: Semiconductor devices are provided. A semiconductor device includes a channel. The semiconductor device includes a gate structure having first and second portions. The channel is between the first and second portions of the gate structure. A contact structure is adjacent a portion of a side surface of the channel. Related methods of forming semiconductor devices are also provided.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: September 3, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Dae Suk, Sunhom Steve Paak, Yeon-Ho Park, Dong-Ho Cha
  • Publication number: 20190252555
    Abstract: A semiconductor device includes a first transistor, a second transistor and a third transistor provided on a substrate, the first to third transistors respectively including source and drain regions spaced apart from each other, a gate structure extending in a first direction on the substrate and interposed between the source and drain regions, and a channel region connecting the source and drain regions to each other. A channel region of the second transistor and a channel region of the third transistor respectively include a plurality of channel portions, the plurality of channel portions spaced apart from each other in a second direction, perpendicular to an upper surface of the substrate, and connected to the source and drain regions, respectively. A width of a channel portion of the third transistor in the first direction is greater than a width of a channel portion of the second transistor in the first direction.
    Type: Application
    Filed: April 26, 2019
    Publication date: August 15, 2019
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Mongsong Liang, Sung-Dae Suk, Geumjong Bae
  • Publication number: 20190229011
    Abstract: A semiconductor device includes: a pair of wire patterns configured to extend in a first direction and formed on a substrate to be spaced apart from each other in a second direction, the pair of wire patterns disposed closest to each other in the second direction; a gate electrode configured to extend in the second direction on the substrate, the gate electrode configured to surround the wire patterns; and first isolation layers configured to extend in the first direction between the substrate and the gate electrode and formed to be spaced apart from each other in the second direction, the first isolation layers overlapping the pair of wire patterns in a third direction perpendicular to the first and second directions.
    Type: Application
    Filed: July 16, 2018
    Publication date: July 25, 2019
    Inventors: Sung Dae SUK, Sang Hoon LEE, Masuoka SADAAKI, Han Su OH
  • Patent number: 10304964
    Abstract: A semiconductor device includes a first transistor, a second transistor and a third transistor provided on a substrate, the first to third transistors respectively including source and drain regions spaced apart from each other, a gate structure extending in a first direction on the substrate and interposed between the source and drain regions, and a channel region connecting the source and drain regions to each other. A channel region of the second transistor and a channel region of the third transistor respectively include a plurality of channel portions, the plurality of channel portions spaced apart from each other in a second direction, perpendicular to an upper surface of the substrate, and connected to the source and drain regions, respectively. A width of a channel portion of the third transistor in the first direction is greater than a width of a channel portion of the second transistor in the first direction.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: May 28, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Mongsong Liang, Sung-Dae Suk, Guemjong Bae
  • Patent number: 10204983
    Abstract: A semiconductor device may include a substrate, a first nanowire, a gate electrode, a first gate spacer, a second gate spacer, a source/drain and a spacer connector. The first nanowire may be extended in a first direction and spaced apart from the substrate. The gate electrode may surround a periphery of the first nanowire, and extend in a second direction intersecting the first direction, and include first and second sidewalls opposite to each other. The first gate spacer may be formed on the first sidewall of the gate electrode. The first nanowire may pass through the first gate spacer. The second gate spacer may be formed on the second sidewall of the gate electrode. The first nanowire may pass through the second gate spacer. The source/drain may be disposed on at least one side of the gate electrode and connected with the first nanowire. The spacer connector may be disposed between the first nanowire and the substrate.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: February 12, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung Dae Suk, Seung Min Song, Geum Jong Bae
  • Publication number: 20190027475
    Abstract: A semiconductor device includes an insulating layer on a substrate, a channel region on the insulating layer, a gate structure on the insulating layer, the gate structure crossing the channel region, source/drain regions on the insulating layer, the source/drain regions being spaced apart from each other with the gate structure interposed therebetween, the channel region connecting the source/drain regions to each other, and contact plugs connected to the source/drain regions, respectively. The channel region includes a plurality of semiconductor patterns that are vertically spaced apart from each other on the insulating layer, the insulating layer includes first recess regions that are adjacent to the source/drain regions, respectively, and the contact plugs include lower portions provided into the first recess regions, respectively.
    Type: Application
    Filed: September 21, 2018
    Publication date: January 24, 2019
    Inventors: Sung-Dae Suk, Jongho Lee, Geumjong Bae
  • Patent number: 10186579
    Abstract: A semiconductor device includes a device isolation layer on a substrate, a first active pattern defined by the device isolation layer, and source/drain regions. The first active pattern extends in a first direction and includes a channel region between a pair of recesses formed at an upper portion of the first active pattern. The source/drain regions fill the pair of recesses in the first active pattern. Each of the source/drain regions include a first semiconductor pattern in the recess and a second semiconductor pattern on the first semiconductor pattern. The source/drain region have an upper portion whose width is less than a width of its lower portion. The second semiconductor pattern has an upper portion whose width is less than a width of its lower portion. The upper portion of the second semiconductor pattern is positioned higher than a top surface of the channel region.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: January 22, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyungseok Min, Sung Dae Suk, JeongYun Lee
  • Patent number: 10128346
    Abstract: A semiconductor device includes a semiconductor pattern on a substrate along a first direction, a blocking pattern on a top surface of the semiconductor pattern, a first wire pattern on the blocking pattern along a second direction different from the first direction, the first wire including a first part and a second part on opposite sides of the first part, a gate electrode surrounding the first part of the first wire pattern, and a contact surrounding the second part of the first wire pattern, wherein a height of a bottom surface of the contact from a top surface of the substrate is different from a height of a bottom surface of the gate electrode from the top surface of the substrate.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: November 13, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ho-Jun Kim, Sung-Dae Suk
  • Patent number: 10109631
    Abstract: A semiconductor device includes an insulating layer on a substrate, a channel region on the insulating layer, a gate structure on the insulating layer, the gate structure crossing the channel region, source/drain regions on the insulating layer, the source/drain regions being spaced apart from each other with the gate structure interposed therebetween, the channel region connecting the source/drain regions to each other, and contact plugs connected to the source/drain regions, respectively. The channel region includes a plurality of semiconductor patterns that are vertically spaced apart from each other on the insulating layer, the insulating layer includes first recess regions that are adjacent to the source/drain regions, respectively, and the contact plugs include lower portions provided into the first recess regions, respectively.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: October 23, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Dae Suk, Jongho Lee, Geumjong Bae
  • Publication number: 20180254341
    Abstract: Semiconductor devices are provided. A semiconductor device includes a channel. The semiconductor device includes a gate structure having first and second portions. The channel is between the first and second portions of the gate structure. A contact structure is adjacent a portion of a side surface of the channel. Related methods of forming semiconductor devices are also provided.
    Type: Application
    Filed: May 3, 2018
    Publication date: September 6, 2018
    Inventors: Sung-Dae Suk, Sunhom Steve Paak, Yeon-Ho Park, Dong-Ho Cha
  • Publication number: 20180212067
    Abstract: A semiconductor device according to example embodiments of inventive concepts may include a substrate, source/drain regions extending perpendicular to an upper surface of the substrate, a plurality of nanosheets on the substrate and separated from each other, and a gate electrode and a gate insulating layer on the substrate. The nanosheets define channel regions that extend in a first direction between the source/drain regions. The gate electrode surrounds the nanosheets and extends in a second direction intersecting the first direction. The gate insulating layer is between the nanosheets and the gate electrode. A length of the gate electrode in the first direction may be greater than a space between adjacent nanosheets among the nanosheets.
    Type: Application
    Filed: March 23, 2018
    Publication date: July 26, 2018
    Applicant: Samsung Electronics Co, Ltd
    Inventors: Jong Ho LEE, Ho Jun Kim, Sung Dae Suk, Geum Jong Bae
  • Publication number: 20180190772
    Abstract: A semiconductor device includes a device isolation layer on a substrate, a first active pattern defined by the device isolation layer, and source/drain regions. The first active pattern extends in a first direction and includes a channel region between a pair of recesses formed at an upper portion of the first active pattern. The source/drain regions fill the pair of recesses in the first active pattern. Each of the source/drain regions include a first semiconductor pattern in the recess and a second semiconductor pattern on the first semiconductor pattern. The source/drain region have an upper portion whose width is less than a width of its lower portion. The second semiconductor pattern has an upper portion whose width is less than a width of its lower portion. The upper portion of the second semiconductor pattern is positioned higher than a top surface of the channel region.
    Type: Application
    Filed: January 4, 2018
    Publication date: July 5, 2018
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Kyungseok MIN, Sung Dae Suk, JeongYun Lee
  • Publication number: 20180175070
    Abstract: A semiconductor device includes a base substrate, a buried insulating film on the base substrate, a first semiconductor substrate pattern on the buried insulating film, a second semiconductor substrate pattern on the buried insulating film, the second semiconductor substrate pattern being spaced apart from the first semiconductor substrate pattern, a first device pattern on the first semiconductor substrate pattern, a second device pattern on the second semiconductor substrate pattern, the first and second device patterns having different characteristics from each other, an isolating trench between the first semiconductor substrate pattern and the second semiconductor substrate pattern, the isolating trench extending only partially into the buried insulating film, and a lower interlayer insulating film overlying the first device pattern and the second device pattern and filling the isolating trench.
    Type: Application
    Filed: December 15, 2017
    Publication date: June 21, 2018
    Inventors: Sung Dae SUK, Geum Jong BAE, Joo Hee JEONG
  • Patent number: 9991387
    Abstract: Semiconductor devices are provided. A semiconductor device includes a channel. The semiconductor device includes a gate structure having first and second portions. The channel is between the first and second portions of the gate structure. A contact structure is adjacent a portion of a side surface of the channel. Related methods of forming semiconductor devices are also provided.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: June 5, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Dae Suk, Sunhom Steve Paak, Yeon-Ho Park, Dong-Ho Cha
  • Patent number: 9985141
    Abstract: A semiconductor device according to example embodiments of inventive concepts may include a substrate, source/drain regions extending perpendicular to an upper surface of the substrate, a plurality of nanosheets on the substrate and separated from each other, and a gate electrode and a gate insulating layer on the substrate. The nanosheets define channel regions that extend in a first direction between the source/drain regions. The gate electrode surrounds the nanosheets and extends in a second direction intersecting the first direction. The gate insulating layer is between the nanosheets and the gate electrode. A length of the gate electrode in the first direction may be greater than a space between adjacent nanosheets among the nanosheets.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: May 29, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong Ho Lee, Ho Jun Kim, Sung Dae Suk, Geum Jong Bae
  • Patent number: 9929160
    Abstract: Disclosed are semiconductor devices including a field effect transistor and methods of manufacturing the same. The semiconductor device comprises a device isolation layer in an upper portion of a substrate, first active patterns on a first region of the substrate and second active patterns on a second region of the substrate, gate structures extending in one direction and running across the first and second active patterns, and a blocking layer on a recessed region of the device isolation layer of the first region. Each of the first and second active patterns comprises a plurality of semiconductor patterns that are vertically stacked and spaced apart from each other. The semiconductor patterns of the first active patterns have conductivity different from that of the semiconductor patterns of the second active patterns. The blocking layer is limited on the first region.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: March 27, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Juri Lee, Yong-Suk Tak, Sung-Dae Suk, Seungmin Song
  • Publication number: 20180083007
    Abstract: Disclosed are semiconductor devices including a field effect transistor and methods of manufacturing the same. The semiconductor device comprises a device isolation layer in an upper portion of a substrate, first active patterns on a first region of the substrate and second active patterns on a second region of the substrate, gate structures extending in one direction and running across the first and second active patterns, and a blocking layer on a recessed region of the device isolation layer of the first region. Each of the first and second active patterns comprises a plurality of semiconductor patterns that are vertically stacked and spaced apart from each other. The semiconductor patterns of the first active patterns have conductivity different from that of the semiconductor patterns of the second active patterns. The blocking layer is limited on the first region.
    Type: Application
    Filed: June 5, 2017
    Publication date: March 22, 2018
    Inventors: Juri LEE, Yong-Suk TAK, Sung-Dae SUK, Seungmin SONG
  • Patent number: 9923058
    Abstract: Provided is a semiconductor device. The semiconductor device includes a fin disposed on a substrate along a first direction. A sacrificial layer is disposed on the fin. An active layer is disposed on the sacrificial layer. A gate insulating layer and a gate electrode are disposed along a second direction intersecting the first direction. The gate insulating layer covers substantially entire top, side and bottom surfaces of the active layer. A source or drain region is disposed on at least one side of the gate electrode on the substrate. A first concentration of germanium in a first region and a second region of the active layer is higher than a second concentration of germanium in a third region disposed between the first region and the second region.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: March 20, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Dae Suk, Kang-Ill Seo