Patents by Inventor Sung-dae Suk

Sung-dae Suk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9679965
    Abstract: A semiconductor device includes a wire pattern spaced apart from a substrate and extended in a first direction, a gate electrode disposed around a circumference of the wire pattern and extended in a second direction that is different from the first direction, a source disposed on a first side of the gate electrode, a drain disposed on a second side of the gate electrode, the source and the drain connected to the wire pattern and a gate spacer disposed on first and second sidewalls of the gate electrode, on the source and on the drain.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: June 13, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung Dae Suk, Bom-Soo Kim, Kang-Ill Seo
  • Publication number: 20170162651
    Abstract: A semiconductor device includes a wire pattern spaced apart from a substrate and extended in a first direction, a gate electrode disposed around a circumference of the wire pattern and extended in a second direction that is different from the first direction, a source disposed on a first side of the gate electrode, a drain disposed on a second side of the gate electrode, the source and the drain connected to the wire pattern and a gate spacer disposed on first and second sidewalls of the gate electrode, on the source and on the drain.
    Type: Application
    Filed: December 7, 2015
    Publication date: June 8, 2017
    Inventors: SUNG-DAE SUK, Bom-Soo Kim, Kang-Ill Seo
  • Publication number: 20170162577
    Abstract: A semiconductor device is provided. A substrate includes a first region and a second region. A first wire pattern, extending in a first direction, is formed at a first height from the substrate of the first region. A second wire pattern, extending in a second direction, is formed at a second height from the substrate of the second region. The first height is different from the second height. A first gate electrode, surrounding the first wire pattern, extends in a third direction crossing the first direction. A second gate electrode, surrounding the second wire pattern, extends in a fourth direction crossing the second direction. A first gate insulation layer is formed along a circumference of the first wire pattern and a sidewall of the first gate electrode. A second gate insulation layer is formed along a circumference of the second wire pattern and a sidewall of the second gate electrode.
    Type: Application
    Filed: February 23, 2017
    Publication date: June 8, 2017
    Inventors: SUNG-DAE SUK, KANG-ILL SEO
  • Patent number: 9653462
    Abstract: A semiconductor device includes a fin type active pattern extended in a first direction and disposed on a substrate. A first gate electrode and a second gate electrode are disposed on the fin type active pattern. The first gate electrode and the second gate electrode are extended in a second direction crossing the first direction. A trench region is disposed in the fin type active pattern and between the first gate electrode and the second gate electrode. A source/drain region is disposed on a surface of the trench region. A source/drain contact is disposed on the source/drain region. The source/drain contact includes a first insulating layer disposed on the source/drain region and a metal oxide layer disposed on the first insulating layer.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: May 16, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Dae Suk, Kang-Ill Seo
  • Patent number: 9613871
    Abstract: A semiconductor device is provided. A substrate includes a first region and a second region. A first wire pattern, extending in a first direction, is formed at a first height from the substrate of the first region. A second wire pattern, extending in a second direction, is formed at a second height from the substrate of the second region. The first height is different from the second height. A first gate electrode, surrounding the first wire pattern, extends in a third direction crossing the first direction. A second gate electrode, surrounding the second wire pattern, extends in a fourth direction crossing the second direction. A first gate insulation layer is formed along a circumference of the first wire pattern and a sidewall of the first gate electrode. A second gate insulation layer is formed along a circumference of the second wire pattern and a sidewall of the second gate electrode.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: April 4, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Dae Suk, Kang-Ill Seo
  • Publication number: 20170092730
    Abstract: A semiconductor device includes a semiconductor pattern on a substrate along a first direction, a blocking pattern on a top surface of the semiconductor pattern, a first wire pattern on the blocking pattern along a second direction different from the first direction, the first wire including a first part and a second part on opposite sides of the first part, a gate electrode surrounding the first part of the first wire pattern, and a contact surrounding the second part of the first wire pattern, wherein a height of a bottom surface of the contact from a top surface of the substrate is different from a height of a bottom surface of the gate electrode from the top surface of the substrate.
    Type: Application
    Filed: May 26, 2016
    Publication date: March 30, 2017
    Inventors: Ho-Jun KIM, Sung-Dae SUK
  • Patent number: 9601569
    Abstract: A semiconductor includes a substrate including a first region and a second region, a fin extending in a first direction in the first region of the substrate, wherein the fin includes a first semiconductor pattern and a second semiconductor pattern that are disposed on each other, a first wire pattern extending in a second direction in the second region of the substrate, a first gate electrode disposed on the fin, wherein the first gate electrode extends in a third direction that is different from the first direction, and a second gate electrode surrounding an outer perimeter of the first wire pattern and extending in a fourth direction that is different from the second direction.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: March 21, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Dae Suk, Kang-Ill Seo
  • Publication number: 20170033102
    Abstract: A semiconductor device includes a plurality of active regions including channel regions extending in a first direction on a semiconductor substrate and source/drain regions connected to the channel regions, a plurality of gate electrodes extending in a second direction different from the first direction to intersect the channel regions, a plurality of conductive lines electrically connected to at least one of the source/drain regions and the plurality of gate electrodes through a plurality of vias, and a power line disposed between the semiconductor substrate and the plurality of conductive lines and configured to supply a power supply voltage.
    Type: Application
    Filed: March 31, 2016
    Publication date: February 2, 2017
    Inventors: Ho Jun Kim, Sung Dae Suk
  • Publication number: 20170018462
    Abstract: A semiconductor device is provided. A substrate includes a first region and a second region. A first wire pattern, extending in a first direction, is formed at a first height from the substrate of the first region. A second wire pattern, extending in a second direction, is formed at a second height from the substrate of the second region. The first height is different from the second height. A first gate electrode, surrounding the first wire pattern, extends in a third direction crossing the first direction. A second gate electrode, surrounding the second wire pattern, extends in a fourth direction crossing the second direction. A first gate insulation layer is formed along a circumference of the first wire pattern and a sidewall of the first gate electrode. A second gate insulation layer is formed along a circumference of the second wire pattern and a sidewall of the second gate electrode.
    Type: Application
    Filed: July 16, 2015
    Publication date: January 19, 2017
    Inventors: Sung-Dae Suk, Kang-lll Seo
  • Publication number: 20170018610
    Abstract: Provided is a semiconductor device. The semiconductor device includes a fin disposed on a substrate along a first direction. A sacrificial layer is disposed on the fin. An active layer is disposed on the sacrificial layer. A gate insulating layer and a gate electrode are disposed along a second direction intersecting the first direction. The gate insulating layer covers substantially entire top, side and bottom surfaces of the active layer. A source or drain region is disposed on at least one side of the gate electrode on the substrate. A first concentration of germanium in a first region and a second region of the active layer is higher than a second concentration of germanium in a third region disposed between the first region and the second region.
    Type: Application
    Filed: June 29, 2016
    Publication date: January 19, 2017
    Inventors: SUNG-DAE SUK, KANG-ILL SEO
  • Publication number: 20170018623
    Abstract: The semiconductor device includes a first wire pattern formed on a substrate and spaced apart from the substrate, the first wire pattern extending in a first direction. A gate electrode surrounds a circumference of the first wire pattern and extends in a second direction. The second direction crosses the first direction. A gate spacer is disposed on opposite sidewalls of the gate electrode, the gate spacer including a first part and a second part. The first part includes a top portion and a bottom portion spaced apart from each other. The second part is disposed at opposite sides of the first part in the second direction. The second part directly contacts the bottom portion of the first part.
    Type: Application
    Filed: July 17, 2015
    Publication date: January 19, 2017
    Inventors: SUNG-DAE SUK, BOM-SOO KIM
  • Publication number: 20170018644
    Abstract: A semiconductor device is provided. A fin is disposed on a substrate. The fin, including a first material and a second material, includes a first fin area and a second fin area. A gate structure is disposed on the first fin area. A source region is in contact with the second fin area. The first fin area includes the first material at a first concentration, the second fin area includes the first material at a second concentration which is greater than the first concentration.
    Type: Application
    Filed: July 15, 2015
    Publication date: January 19, 2017
    Inventors: SUNG-DAE SUK, Kang-Ill Seo
  • Publication number: 20160365440
    Abstract: Semiconductor devices are provided. A semiconductor device includes a channel. The semiconductor device includes a gate structure having first and second portions. The channel is between the first and second portions of the gate structure. A contact structure is adjacent a portion of a side surface of the channel. Related methods of forming semiconductor devices are also provided.
    Type: Application
    Filed: June 3, 2016
    Publication date: December 15, 2016
    Inventors: SUNG-DAE SUK, SUNHOM STEVE PAAK, YEON-HO PARK, DONG-HO CHA
  • Patent number: 9431522
    Abstract: A method of manufacturing a semiconductor device includes patterning a substrate to form an active fin, forming a sacrificial gate pattern crossing over the active fin on the substrate, forming an interlayer insulating layer on the sacrificial gate pattern, removing the sacrificial gate pattern to form a gap region exposing the active fin in the interlayer insulating layer, and oxidizing a portion of the active fin exposed by the gap region to form an insulation pattern between the active fin and the substrate.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: August 30, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sungmin Kim, Sung-Dae Suk, Jaehoo Park, Dongho Cha, Daewon Ha
  • Patent number: 9425259
    Abstract: Provided is a semiconductor device. The semiconductor device includes a fin disposed on a substrate along a first direction. A sacrificial layer is disposed on the fin. An active layer is disposed on the sacrificial layer. A gate insulating layer and a gate electrode are disposed along a second direction intersecting the first direction. The gate insulating layer covers substantially entire top, side and bottom surfaces of the active layer. A source or drain region is disposed on at least one side of the gate electrode on the substrate. A first concentration of germanium in a first region and a second region of the active layer is higher than a second concentration of germanium in a third region disposed between the first region and the second region.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: August 23, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Dae Suk, Kang-Ill Seo
  • Patent number: 9412849
    Abstract: A method of fabricating a semiconductor device includes forming first and second fin-type structures on first and second regions of a substrate, respectively, forming first and second capping layers on the first and second fin-type structures, respectively, forming a first dummy gate electrode on the first capping layer and a second dummy gate electrode on the second capping layer, exposing the first capping layer and the second capping layer by removing the first dummy gate electrode and the second dummy gate electrode, forming a second wire pattern group on the second region, and forming a first wire pattern group on the first region.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: August 9, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Dae Suk, Dong-Il Bae
  • Publication number: 20160190239
    Abstract: A semiconductor device is provided. The semiconductor device includes a sacrificial layer formed on a substrate, an active layer formed on the sacrificial layer, a gate insulating layer and a gate electrode formed to surround a part of the active layer, a spacer disposed on at least one side of the gate electrode, a source or drain separated from the gate electrode by the spacer and disposed on the substrate, and an air gap arrange between a lower portion of the active layer and the sacrificial layer, wherein the sacrificial layer is disposed on a lower portion of the source or drain and is not disposed on a lower portion of the gate electrode.
    Type: Application
    Filed: December 26, 2014
    Publication date: June 30, 2016
    Inventors: Sung-Dae SUK, Kang-III SEO
  • Publication number: 20160190128
    Abstract: A semiconductor device includes a fin type active pattern extended in a first direction and disposed on a substrate. A first gate electrode and a second gate electrode are disposed on the fin type active pattern. The first gate electrode and the second gate electrode are extended in a second direction crossing the first direction. A trench region is disposed in the fin type active pattern and between the first gate electrode and the second gate electrode. A source/drain region is disposed on a surface of the trench region. A source/drain contact is disposed on the source/drain region. The source/drain contact includes a first insulating layer disposed on the source/drain region and a metal oxide layer disposed on the first insulating layer.
    Type: Application
    Filed: December 26, 2014
    Publication date: June 30, 2016
    Inventors: Sung-Dae Suk, Kang-III Seo
  • Patent number: 9362311
    Abstract: A method of fabricating a semiconductor device is provided. A first semiconductor layer including Ge at a first concentration is formed on an insulation layer. Second and third semiconductor layers are formed sequentially on the first semiconductor layer. The second and third semiconductor layers include Ge at second and third concentrations higher than the first concentration. A fin type structure is formed by patterning the insulation layer and the first to third semiconductor layers. The fin type structure is vertically protruded. A fin type active pattern is formed on the fin type structure by performing a first thermal process on the fin type structure. The fin type active pattern includes Ge at a fourth concentration higher than the first concentration and lower than the second concentration.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: June 7, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Dae Suk, Kang-Ill Seo
  • Publication number: 20160141392
    Abstract: A method of manufacturing a semiconductor device includes patterning a substrate to form an active fin, forming a sacrificial gate pattern crossing over the active fin on the substrate, forming an interlayer insulating layer on the sacrificial gate pattern, removing the sacrificial gate pattern to form a gap region exposing the active fin in the interlayer insulating layer, and oxidizing a portion of the active fin exposed by the gap region to form an insulation pattern between the active fin and the substrate.
    Type: Application
    Filed: January 21, 2016
    Publication date: May 19, 2016
    Inventors: SUNGMIN KIM, SUNG-DAE SUK, JAEHOO PARK, DONGHO CHA, DAEWON HA