Patents by Inventor Sung-Feng Yeh

Sung-Feng Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250069985
    Abstract: A method includes bonding a bottom die to a carrier, and bonding a top die to the bottom die. The top die includes a semiconductor substrate, and the semiconductor substrate has a first thermal conductivity. The method further includes encapsulating the top die in a gap-fill region, bonding a supporting substrate to the top die and the gap-fill region to form a reconstructed wafer, wherein the supporting substrate has a second thermal conductivity higher than the first thermal conductivity, de-bonding the reconstructed wafer from the carrier, and forming electrical connectors on the bottom die.
    Type: Application
    Filed: December 18, 2023
    Publication date: February 27, 2025
    Inventors: Kuo-Chiang Ting, Sung-Feng Yeh, Ta Hao Sung, Jian-Wei Hong
  • Publication number: 20250062289
    Abstract: A package includes a first die, a second die, a first encapsulant, first through insulating vias (TIV), second encapsulant, and second TIVs. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The first TIVs are aside the first die. The first TIVs penetrate through the first encapsulant and are electrically floating. The second encapsulant laterally encapsulates the second die. The second TIVs are aside the second die. The second TIVs penetrate through the second encapsulant and are electrically floating. The second TIVs are substantially aligned with the first TIVs.
    Type: Application
    Filed: November 3, 2024
    Publication date: February 20, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Jian-Wei Hong
  • Publication number: 20250054926
    Abstract: A semiconductor package with two interposers, and the method of forming the same are provided. The semiconductor package may include a first interposer, a first semiconductor die on the first interposer, a second interposer on the first semiconductor die, and a second semiconductor die on the second interposer. The second interposer may be between the first semiconductor die and the second semiconductor die. The first semiconductor die may be bonded to the first interposer by metal-to-metal bonding and dielectric-to-dielectric bonding. The second semiconductor die may be bonded to the second interposer by metal-to-metal bonding and dielectric-to-dielectric bonding.
    Type: Application
    Filed: August 11, 2023
    Publication date: February 13, 2025
    Inventors: Hsien-Wei Chen, Sung-Feng Yeh
  • Patent number: 12224265
    Abstract: A stacking structure including a first die, a second die stacked on the first die, and a third die and a fourth die disposed on the second die. The first die has a first metallization structure, and the first metallization structure includes first through die vias. The second die has a second metallization structure, and second metallization structure includes second through die vias. The first through die vias are bonded with the second through die vias, and sizes of the first through die vias are different from sizes of the second through die vias. The third and fourth dies are disposed side-by-side and are bonded with the second through die vias.
    Type: Grant
    Filed: July 1, 2022
    Date of Patent: February 11, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih
  • Patent number: 12218026
    Abstract: A package structure and method of manufacturing is provided, whereby heat dissipating features are provided for heat dissipation. Heat dissipating features include conductive vias formed in a die stack, thermal chips, and thermal metal bulk, which can be bonded to a wafer level device. Hybrid bonding including chip to chip, chip to wafer, and wafer to wafer provides thermal conductivity without having to traverse a bonding material, such as a eutectic material. Plasma dicing the package structure can provide a smooth sidewall profile for interfacing with a thermal interface material.
    Type: Grant
    Filed: June 12, 2023
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Sung-Feng Yeh, Ming-Fa Chen
  • Publication number: 20250040254
    Abstract: A package structure including a bottom die, a first die, a second die, an encapsulant and a first dummy structure is provided. The first die and a second die are bonded to a first side of the bottom die. The encapsulant laterally encapsulates the first die and the second die. The first dummy structure is bonded to the first side of the bottom die, wherein a sidewall of the first dummy structure is coplanar with a first sidewall of the bottom die.
    Type: Application
    Filed: October 15, 2024
    Publication date: January 30, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih
  • Patent number: 12211823
    Abstract: A package structure includes first and second dies, an insulation structure, a through via, a dielectric layer and a redistribution layer. The second die electrically bonded to the first die includes a through substrate via. The insulation structure is disposed on the first die and laterally surrounds the second die. The through via penetrates through the insulation structure to electrically connect to the first die. The dielectric layer is disposed on the second die and the insulation structure. The redistribution layer is embedded in the dielectric layer and electrically connected to the through via. The redistribution layer includes a first barrier layer and a conductive layer on the first barrier layer. The through substrate via is electrically connected to the redistribution layer, and the conductive layer is in contact with a conductive post of the through via and separated from the through substrate via by the first barrier layer therebetween.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: January 28, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Ching-Jung Yang, Ming-Fa Chen, Sung-Feng Yeh, Ying-Ju Chen
  • Patent number: 12205911
    Abstract: A package includes a first die that includes a first metallization layer, one or more first bond pad vias on the first metallization layer, wherein a first barrier layer extends across the first metallization layer between each first bond pad via and the first metallization layer, and one or more first bond pads on the one or more first bond pad vias, wherein a second barrier layer extends across each first bond pad via between a first bond pad and the first bond pad via, and a second die including one or more second bond pads, wherein a second bond pad is bonded to a first bond pad of the first die.
    Type: Grant
    Filed: July 24, 2023
    Date of Patent: January 21, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Hsien-Wei Chen, Jie Chen
  • Patent number: 12199024
    Abstract: A semiconductor device and method of manufacture are presented in which a first semiconductor device and second semiconductor device are bonded to a first wafer and then singulated to form a first package and a second package. The first package and second package are then encapsulated with through interposer vias, and a redistribution structure is formed over the encapsulant. A separate package is bonded to the through interposer vias.
    Type: Grant
    Filed: August 5, 2022
    Date of Patent: January 14, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Sung-Feng Yeh, Ming-Fa Chen, Hsien-Wei Chen, Tzuan-Horng Liu
  • Publication number: 20250006587
    Abstract: A semiconductor package with a dummy die having two layers with different thermal conductivities and the method of forming the same are provided. The semiconductor package may include a first semiconductor die, a first bonding layer on the first semiconductor die, a second semiconductor die bonded to the first bonding layer, and a first dummy die bonded to the first bonding layer. The first dummy die may include a substrate, a material layer between the substrate and the first bonding layer, and a second bonding layer between the material layer and the first bonding layer. The material layer may include a first material with a first thermal conductivity and the second bonding layer may include a second material with a second thermal conductivity different from the first thermal conductivity.
    Type: Application
    Filed: June 27, 2023
    Publication date: January 2, 2025
    Inventors: Kuo-Chiang Ting, Sung-Feng Yeh, Ta Hao Sung, Shu-Yan Jhu
  • Patent number: 12170264
    Abstract: Provided are integrated circuit packages and methods of forming the same. An integrated circuit package includes an integrated circuit structure, a first die stack and a dummy die. The first die stack includes a plurality of first die structures and is bonded to the integrated circuit structure at a first side of the first die stack. The dummy die includes a plurality of through substrate vias, is located aside the first die stack and is electrically connected to the integrated circuit structure at the first side of the first die stack. In some embodiments, the height of the through substrate vias of the dummy die is the same as the height of the first die stack.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: December 17, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chia Hu, Ming-Fa Chen, Sung-Feng Yeh
  • Patent number: 12166014
    Abstract: A manufacturing method of a package includes at least the following steps. Contact vias are embedded in a semiconductor carrier. The contact vias are electrically grounded. A first die and a first encapsulant are provided over the semiconductor carrier. The first encapsulant encapsulates the first die. First through insulating vias (TIV) are formed aside the first die. The first TIVs are electrically grounded through the contact vias. The first die, the first encapsulant, and the first TIVs are grinded. A second die is stacked over the first die.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: December 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Jian-Wei Hong
  • Patent number: 12154897
    Abstract: A package structure including a bottom die, a first die, a second die, an encapsulant and a first dummy structure is provided. The first die and a second die are bonded to a first side of the bottom die. The encapsulant laterally encapsulates the first die and the second die. The first dummy structure is bonded to the first side of the bottom die, wherein a sidewall of the first dummy structure is coplanar with a first sidewall of the bottom die.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: November 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih
  • Publication number: 20240387452
    Abstract: A package structure and method of manufacturing is provided, whereby a bonding dielectric material layer is provided at a back side of a wafer, a bonding dielectric material layer is provided at a front side of an adjoining wafer, and wherein the bonding dielectric material layers are fusion bonded to each other.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Inventors: Ming-Fa Chen, Chao-Wen Shih, Sung-Feng Yeh
  • Publication number: 20240379501
    Abstract: A package structure including a first semiconductor die, a first insulating encapsulation, a bonding enhancement film, a second semiconductor die and a second insulating encapsulation is provided. The first insulating encapsulation laterally encapsulates a first portion of the first semiconductor die. The bonding enhancement film is disposed on a top surface of the first insulating encapsulation and laterally encapsulates a second portion of the first semiconductor die, wherein a top surface of the bonding enhancement film is substantially leveled with a top surface of the semiconductor die. The second semiconductor die is disposed on and bonded to the first semiconductor die and the bonding enhancement film. The second insulating encapsulation laterally encapsulates the second semiconductor die.
    Type: Application
    Filed: July 16, 2024
    Publication date: November 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Jie Chen, Ming-Fa Chen, Sung-Feng Yeh
  • Publication number: 20240379598
    Abstract: A package includes a first die that includes a first metallization layer, one or more first bond pad vias on the first metallization layer, wherein a first barrier layer extends across the first metallization layer between each first bond pad via and the first metallization layer, and one or more first bond pads on the one or more first bond pad vias, wherein a second barrier layer extends across each first bond pad via between a first bond pad and the first bond pad via, and a second die including one or more second bond pads, wherein a second bond pad is bonded to a first bond pad of the first die.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Hsien-Wei Chen, Jie Chen
  • Publication number: 20240379614
    Abstract: In a method, a wafer is bonded to a first carrier. The wafer includes a semiconductor substrate, and a first plurality of through-vias extending into the semiconductor substrate. The method further includes bonding a plurality of chips over the wafer, with gaps located between the plurality of chips, performing a gap-filling process to form gap-filling regions in the gaps, bonding a second carrier onto the plurality of chips and the gap-filling regions, de-bonding the first carrier from the wafer, and forming electrical connectors electrically connecting to conductive features in the wafer. The electrical connectors are electrically connected to the plurality of chips through the first plurality of through-vias.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Inventors: Ming-Fa Chen, Cheng-Feng Chen, Sung-Feng Yeh, Chuan-An Cheng
  • Publication number: 20240371833
    Abstract: A package structure includes a first die, a die stack structure bonded to the first die, a support structure and an insulation structure. The support structure is disposed on the die stack structure, and a sidewall of the support structure is laterally shifted from a sidewall of the die stack structure. The insulation structure is disposed on the first die and laterally wraps around the die stack structure and the support structure.
    Type: Application
    Filed: July 16, 2024
    Publication date: November 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih
  • Publication number: 20240371826
    Abstract: A package includes a first package structure and a second package structure stacked on and electrically connected to the first package structure. The first package structure includes an integrated circuit, conductive structures, and an encapsulant. The integrated circuit includes a first chip, a second chip, a third chip, and a fourth chip. The first chip includes a semiconductor substrate. The second and the third chips are disposed side by side on the first chip. The fourth chip is disposed over the first chip and includes a semiconductor substrate. Sidewalls of the semiconductor substrate of the first chip are aligned with sidewalls of the semiconductor substrate of the fourth chip. The encapsulant laterally encapsulates the integrated circuit and the conductive structures. A topmost surface of the encapsulant is coplanar with top surfaces of the conductive structures. A bottommost surface of the encapsulant is coplanar with bottom surfaces of the conductive structures.
    Type: Application
    Filed: July 21, 2024
    Publication date: November 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih
  • Publication number: 20240371852
    Abstract: A method of manufacturing a semiconductor device includes the following steps. A gap is formed. A first dielectric layer is formed in the gap, wherein the first dielectric layer has a sidewall and a bottom, a first surface of the sidewall and a first surface of the bottom form a first angle, and a second angle smaller than the first angle is formed by a second surface of the sidewall and a second surface of the bottom.
    Type: Application
    Filed: July 16, 2024
    Publication date: November 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Ming-Fa Chen, Sung-Feng Yeh