Patents by Inventor Sung-Haeng Cho

Sung-Haeng Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150311234
    Abstract: A thin film transistor array panel includes: a gate line disposed on a substrate and including a gate electrode, a semiconductor layer including an oxide semiconductor disposed on the substrate, and a data wire layer disposed on the substrate and including a data line intersecting the gate line, a source electrode connected to the data line, and a drain electrode facing the source electrode. In addition, at least one of the data line, the source electrode or the drain electrode of the data wire layer includes a barrier layer and a main wiring layer disposed on the barrier layer. The main wiring layer includes copper or a copper alloy. Also, the barrier layer includes a metal oxide, and the metal oxide includes zinc.
    Type: Application
    Filed: July 9, 2015
    Publication date: October 29, 2015
    Inventors: Jae Woo PARK, Do-Hyun KIM, Young Joo CHOI, Dong Hoon LEE, Sung Haeng CHO
  • Publication number: 20150287836
    Abstract: A Thin Film Transistor (TFT) includes a substrate, a semiconductor layer disposed on the substrate a first source electrode and a first drain electrode spaced apart from each other on the semiconductor layer, a channel area disposed in the semiconductor layer between the first source electrode and the first drain electrode, an etching prevention layer disposed on the channel area, the first source electrode, and the first drain electrode and a second source electrode in contact with the first source electrode, and a second drain electrode in contact with the first drain electrode.
    Type: Application
    Filed: June 18, 2015
    Publication date: October 8, 2015
    Inventors: Hyun-Jung Lee, Sung-Haeng Cho, Woo-Geun Lee, Jang-Hoon Ha, Hee-Jun Byeon, Ji-Yun Hong, Ji-Soo Oh
  • Patent number: 9117917
    Abstract: A Thin Film Transistor (TFT) includes a substrate, a semiconductor layer disposed on the substrate a first source electrode and a first drain electrode spaced apart from each other on the semiconductor layer, a channel area disposed in the semiconductor layer between the first source electrode and the first drain electrode, an etching prevention layer disposed on the channel area, the first source electrode, and the first drain electrode and a second source electrode in contact with the first source electrode, and a second drain electrode in contact with the first drain electrode.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: August 25, 2015
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Hyun-Jung Lee, Sung-Haeng Cho, Woo-Geun Lee, Jang-Hoon Ha, Hee-Jun Byeon, Ji-Yun Hong, Ji-Soo Oh
  • Patent number: 9105726
    Abstract: Provided is a transistor. The transistor includes: a substrate; a semiconductor layer provided on the substrate and having one side vertical to the substrate and the other side facing the one side; a first electrode extending along the substrate and contacting the one side of the semiconductor layer; a second electrode extending along the substrate and contacting the other side of the semiconductor layer; a conductive wire disposed on the first electrode and spaced from the second electrode; a gate electrode provided on the semiconductor layer; and a gate insulating layer disposed between the semiconductor layer and the gate electrode, wherein the semiconductor layer, the first electrode, and the second electrode have a coplanar.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: August 11, 2015
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung Haeng Cho, Sang-Hee Park, Chi-Sun Hwang
  • Patent number: 9099438
    Abstract: A thin film transistor array panel includes: a gate line disposed on a substrate and including a gate electrode, a semiconductor layer including an oxide semiconductor disposed on the substrate, and a data wire layer disposed on the substrate and including a data line intersecting the gate line, a source electrode connected to the data line, and a drain electrode facing the source electrode. In addition, at least one of the data line, the source electrode or the drain electrode of the data wire layer includes a barrier layer and a main wiring layer disposed on the barrier layer. The main wiring layer includes copper or a copper alloy. Also, the barrier layer includes a metal oxide, and the metal oxide includes zinc.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: August 4, 2015
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jae Woo Park, Do-Hyun Kim, Young Joo Choi, Dong Hoon Lee, Sung Haeng Cho
  • Patent number: 9070718
    Abstract: A thin film transistor, a display device, and a manufacturing method thereof. The thin film transistor includes a control electrode, a semiconductor overlapping the control electrode, and an input electrode and an output electrode disposed on or under the semiconductor and opposite to each other. The semiconductor includes a first portion disposed between the input electrode and the output electrode and having a first crystallinity, and a second portion connected with the first portion, which overlaps the input electrode or the output electrode, and having a second crystallinity. The first crystallinity is higher than the second crystallinity.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: June 30, 2015
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Sung-Haeng Cho, Ki-Hun Jeong, Jun-Ho Song, Joo-Han Kim, Hyung-Jun Kim, Seung-Hwan Shim
  • Patent number: 9018623
    Abstract: An array substrate includes a thin film transistor which includes a gate electrode electrically connected to a gate line, a source electrode electrically connected to a data line, a drain electrode and an active layer, a first electrode electrically connected to the drain electrode and disposed at a pixel area, and a second electrode covering an upper and a side surface of the source electrode. The second electrode is spaced apart from the first electrode.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: April 28, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Duk-Sung Kim, Sung-Haeng Cho
  • Patent number: 8952876
    Abstract: A display substrate includes a base substrate, a first insulating layer formed on a base substrate, a pixel including a pixel electrode having the first insulating layer, and a circuit including a circuit transistor disposed on a peripheral area to drive the pixel. The pixel includes a first channel formed on the base substrate having the first insulating layer formed thereon. The first channel includes a poly-silicon layer, a first source electrode and a first drain electrode formed on the first channel that are spaced apart from each other, and a first gate electrode formed on the first source electrode and the first drain electrode corresponding to the first channel which is formed of the transparent conductive material. The poly-silicon layer is formed at a front channel portion of the first channel proximal to the first gate electrode through the first gate electrode.
    Type: Grant
    Filed: October 8, 2010
    Date of Patent: February 10, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hyung-Jun Kim, Sung-Haeng Cho, Yong-Mo Choi
  • Publication number: 20140367689
    Abstract: Provided is a transistor. The transistor includes: a substrate; a semiconductor layer provided on the substrate and having one side vertical to the substrate and the other side facing the one side; a first electrode extending along the substrate and contacting the one side of the semiconductor layer; a second electrode extending along the substrate and contacting the other side of the semiconductor layer; a conductive wire disposed on the first electrode and spaced from the second electrode; a gate electrode provided on the semiconductor layer; and a gate insulating layer disposed between the semiconductor layer and the gate electrode, wherein the semiconductor layer, the first electrode, and the second electrode have a coplanar.
    Type: Application
    Filed: February 27, 2014
    Publication date: December 18, 2014
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Sung Haeng CHO, Sang-Hee PARK, Chi-Sun HWANG
  • Patent number: 8755019
    Abstract: A method of manufacturing a liquid crystal display includes: forming a gate line including a gate electrode on a first substrate; forming a gate insulating layer on the gate line; sequentially forming a semiconductor layer, an amorphous silicon layer, and a data metal layer on the entire surface of the gate insulating layer; aligning the edges of the semiconductor layer and the data metal layer; forming a transparent conductive layer on the gate insulating layer and the data metal layer; forming a first pixel electrode and a second pixel electrode by patterning the transparent conductive layer; and forming a data line including a source electrode, a drain electrode, and an ohmic contact layer by etching the data metal layer and the amorphous silicon layer, using the first pixel electrode and the second pixel electrode as a mask, and exposing the semiconductor between the source electrode and the drain electrode.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: June 17, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Ji-Young Park, Sang Gab Kim, Yong-Mo Choi, Hyung Jun Kim, Sung-Haeng Cho, Hong-Sick Park, Byeong-Jin Lee, Soo-Wan Yoon
  • Patent number: 8735890
    Abstract: In a display substrate and a method of manufacturing the display substrate, the display substrate includes a data line, a channel pattern, an insulating pattern and a pixel electrode. The data line extends in a direction on a base substrate. The channel pattern is disposed in a separate region between an input electrode connected to the data line and an output electrode spaced apart from the input electrode. The channel pattern makes contact with the input electrode and the output electrode on the input and output electrodes. The insulating pattern is spaced apart from the channel pattern on the base substrate and includes a contact hole exposing the output electrode. The pixel electrode is formed on the insulating pattern to make contact with the output electrode through the contact hole. Thus, a damage of the oxide semiconductor layer may be minimized and a manufacturing process may be simplified.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: May 27, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Ki-Won Kim, Je-Hun Lee, Sung-Haeng Cho, Woo-Geun Lee, Kap-Soo Yoon, Do-Hyun Kim, Seung-Ha Choi
  • Publication number: 20140001463
    Abstract: An array substrate includes a thin film transistor which includes a gate electrode electrically connected to a gate line, a source electrode electrically connected to a data line, a drain electrode and an active layer, a first electrode electrically connected to the drain electrode and disposed at a pixel area, and a second electrode covering an upper and a side surface of the source electrode. The second electrode is spaced apart from the first electrode.
    Type: Application
    Filed: November 12, 2012
    Publication date: January 2, 2014
    Applicant: Samsung Display Co., Ltd.
    Inventors: Duk-Sung KIM, Sung-Haeng Cho
  • Patent number: 8598577
    Abstract: A display substrate includes a gate line extending in a first direction on a base substrate, a data line on the base substrate and extending in a second direction crossing the first direction, a gate insulating layer on the gate line, a thin-film transistor and a pixel electrode. The thin-film transistor includes a gate electrode electrically connected the gate line, an oxide semiconductor pattern, and source and drain electrodes on the oxide semiconductor pattern and spaced apart from each other. The oxide semiconductor pattern includes a first semiconductor pattern including indium oxide and a second semiconductor pattern including indium-free oxide. The pixel electrode is electrically connected the drain electrode.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: December 3, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jae-Woo Park, Dong-Hoon Lee, Sung-Haeng Cho, Woo-Geun Lee, Hye-Young Ryu, Young-Joo Choi
  • Publication number: 20130299817
    Abstract: A thin film transistor array panel includes: a gate line disposed on a substrate and including a gate electrode, a semiconductor layer including an oxide semiconductor disposed on the substrate, and a data wire layer disposed on the substrate and including a data line intersecting the gate line, a source electrode connected to the data line, and a drain electrode facing the source electrode. In addition, at least one of the data line, the source electrode or the drain electrode of the data wire layer includes a barrier layer and a main wiring layer disposed on the barrier layer. The main wiring layer includes copper or a copper alloy. Also, the barrier layer includes a metal oxide, and the metal oxide includes zinc.
    Type: Application
    Filed: October 25, 2012
    Publication date: November 14, 2013
    Applicant: Samsung Display Co., Ltd.
    Inventors: Jae Woo PARK, Do-Hyun Kim, Young Joo Choi, Dong Hoon Lee, Sung Haeng Cho
  • Publication number: 20130260498
    Abstract: A thin film transistor, a display device, and a manufacturing method thereof. The thin film transistor includes a control electrode, a semiconductor overlapping the control electrode, and an input electrode and an output electrode disposed on or under the semiconductor and opposite to each other. The semiconductor includes a first portion disposed between the input electrode and the output electrode and having a first crystallinity, and a second portion connected with the first portion, which overlaps the input electrode or the output electrode, and having a second crystallinity. The first crystallinity is higher than the second crystallinity.
    Type: Application
    Filed: May 22, 2013
    Publication date: October 3, 2013
    Applicant: Samsung Display Co., Ltd.
    Inventors: Sung-Haeng CHO, Ki-Hun JEONG, Jun-Ho SONG, Joo-Han Kim, Hyung-Jun Kim, Seung-Hwan SHIM
  • Patent number: 8450742
    Abstract: A thin film transistor, a display device, and a manufacturing method thereof. The thin film transistor includes a control electrode, a semiconductor overlapping the control electrode, and an input electrode and an output electrode disposed on or under the semiconductor and opposite to each other. The semiconductor includes a first portion disposed between the input electrode and the output electrode and having a first crystallinity, and a second portion connected with the first portion, which overlaps the input electrode or the output electrode, and having a second crystallinity. The first crystallinity is higher than the second crystallinity.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: May 28, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sung-Haeng Cho, Ki-Hun Jeong, Jun-Ho Song, Joo-Han Kim, Hyung-Jun Kim, Seung-Hwan Shim
  • Patent number: 8450850
    Abstract: Provided are a thin-film transistor (TFT) substrate and a method of manufacturing the same. The method includes: forming a passivation film by forming an insulating film on a substrate; forming a photoresist pattern by forming a photoresist film on the passivation film, exposing the photoresist film to light, and developing the photoresist film; performing a first dry-etching by dry-etching the passivation film using the photoresist pattern as an etch mask; performing a baking to reduce a size of the photoresist pattern; performing a second dry-etching to form a contact hole by dry-etching the passivation film again using the photoresist pattern as a mask; removing the photoresist pattern; and forming a pixel electrode of a carbon composition that includes carbon nanotubes and/or graphene on a top surface of the passivation film.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: May 28, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hong Long Ning, Chang-Oh Jeong, Ji-Young Park, Sang-Gab Kim, Sung-Haeng Cho, Yeon-Hong Kim, Jin-Su Byun
  • Publication number: 20130099240
    Abstract: A Thin Film Transistor (TFT) includes a substrate, a semiconductor layer disposed on the substrate a first source electrode and a first drain electrode spaced apart from each other on the semiconductor layer, a channel area disposed in the semiconductor layer between the first source electrode and the first drain electrode, an etching prevention layer disposed on the channel area, the first source electrode, and the first drain electrode and a second source electrode in contact with the first source electrode, and a second drain electrode in contact with the first drain electrode.
    Type: Application
    Filed: October 12, 2012
    Publication date: April 25, 2013
    Applicant: Samsung Display Co., Ltd.
    Inventors: Hyun-Jung LEE, Sung-Haeng CHO, Woo-Geun LEE, Jang-Hoon HA, Hee-Jun BYEON, Ji-Yun HONG, Ji-Soo OH
  • Publication number: 20130032793
    Abstract: Provided is a thin film transistor array panel. The thin film transistor array panel according to exemplary embodiments of the present invention includes: a gate wiring layer disposed on a substrate; an oxide semiconductor layer disposed on the gate wiring layer; and a data wiring layer disposed on the oxide semiconductor layer, in which the data wiring layer includes a main wiring layer including copper and a capping layer disposed on the main wiring layer and including a copper alloy.
    Type: Application
    Filed: February 6, 2012
    Publication date: February 7, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Do-Hyun KIM, Yoon Ho KHANG, Dong-Hoon LEE, Sang Ho PARK, Se Hwan YU, Cheol Kyu KIM, Yong-Su LEE, Sung-Haeng CHO, Chong Sup CHANG, Dong Jo KIM, Jung Kyu LEE
  • Publication number: 20120319112
    Abstract: A thin film transistor includes a gate electrode, a gate insulating layer, an oxide semiconductor layer on the gate insulating layer, and a drain electrode and a source electrode on the oxide semiconductor layer and spaced apart from each other. The drain electrode includes a first drain sub-electrode on the oxide semiconductor layer, and a second drain sub-electrode on the first drain sub-electrode. The source electrode includes a first source sub-electrode on the oxide semiconductor layer, and a second source sub-electrode on the first source sub-electrode. The first drain sub-electrode and the first source sub-electrode include gallium zinc oxide (GaZnO), and the second source sub-electrode and the second drain sub-electrode include a metal atom.
    Type: Application
    Filed: September 1, 2011
    Publication date: December 20, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Haeng CHO, Jae-Woo PARK, Do-Hyun KIM