Abstract: Disclosed are a flash memory device and a method of manufacturing the same. In the method of manufacturing the flash memory device, gate patterns of a cell area and a logic area are formed by sequentially depositing and patterning a first polysilicon layer, an ONO layer and a second polysilicon layer without separately performing a photolithography process for one of the gate patterns. A mask process for removing a dummy gate pattern in the logic area is performed to form transistors in the cell area and the logic area, so that the manufacturing process is simplified.

Abstract: A method for manufacturing a three-dimensional high voltage transistor is disclosed. According to the method, lengths and widths of channels are increased while the reducing transistor forming area on plane, and semiconductor devices are completely separated from each other while restraining parasitic capacitance, latch-up phenomena, and formation of field transistors. The three-dimensional high voltage transistor includes an active area of the three-dimensional high voltage transistor formed in the form of a column on predetermined areas of a Silicon-On-Insulator substrate, source and drain formed in the active areas of the three-dimensional high voltage transistor in the depth direction, a channel area formed between the source and the drain in the depth direction, and a column-shaped gate formed at the side of the channel area on the Silicon-On-Insulator substrate.

Abstract: Disclosed are a semiconductor device and a method of manufacturing the same. The semiconductor device includes a semiconductor substrate having source and drain areas; a floating gate between the source and drain areas having a programmed or erased state, thereby controlling a current flow between the source and drain areas; and a tunneling gate adapted to program or erase the floating gate depending on voltage(s) applied to the source, drain and/or tunneling gate.

Abstract: The flash cell includes a silicon substrate; a floating gate formed on a predetermined area of the silicon substrate; a control gate formed on the floating gate and the silicon substrate; a piezoelectric layer formed on the control gate; and an upper electrode formed on the piezoelectric layer. The flash cell brings the control gate in contact with the floating gate, instead of electrically removing electrons contained in the floating gate, resulting in a charge equilibrium state. Therefore, the flash cell completely solves the over-erasing problem. If a voltage signal is applied to the flash cell, the flash cell uses the displacement of piezoelectric/electrostrictive materials. The displacement occurs according to the received voltage, such that the flash cell implements at high speed compared to conventional electric erasing methods.