Abstract: A three-dimensional memory device includes a first electrode structure and a second electrode structure extending in a first direction, being adjacent to each other in a second direction intersecting with the first direction, and each including a plurality of electrode layers and a plurality of interlayer dielectric layers which are alternately stacked on a source plate; a plurality of first slimming holes formed in the first electrode structure to expose pad regions of the electrode layers of the first electrode structure, and arranged in the first direction; and a plurality of second slimming holes formed in the second electrode structure to expose pad regions of the electrode layers of the second electrode structure, and arranged in the first direction, wherein a first slimming hole and a second slimming hole which are adjacent in the second direction have different depths.

Abstract: A memory device includes a cell wafer having a first pad on one surface thereof; and a peripheral wafer bonded to the one surface of the cell wafer, and having a second pad coupled to the first pad. The cell wafer includes a memory cell array; first and second bit lines coupled to the memory cell array; and a bit line selection circuit configured to couple one of the first and second bit lines to the first pad. The peripheral wafer includes a page buffer low-voltage circuit including a first page buffer low-voltage unit corresponding to the first bit line and a second page buffer low-voltage unit corresponding to the second bit line; and a page buffer high-voltage circuit configured to couple one of the first and second page buffer low-voltage units to the second pad.

Abstract: A semiconductor memory device with a three-dimensional (3D) structure may include: a cell region arranged over a substrate, including a cell structure; a peripheral circuit region arranged between the substrate and the cell region; an upper wiring structure arranged over the cell region; main channel films and dummy channel films formed through the cell structure. The dummy channel films are suitable for electrically coupling the upper wiring structure.

Abstract: A semiconductor device includes a first connection pattern; a bit line disposed over the first connection pattern in a vertical direction; and a bit-line contact pad, disposed in a first layer between the bit line and the first connection pattern to electrically couple the bit line to the first connection pattern, and formed as an island when viewed along the vertical direction. A predetermined number of the bit-line contact pads are spaced apart from each other by a predetermined distance in a first direction, when viewed along the vertical direction.

Abstract: A semiconductor memory device includes a plurality of planes defined in a plurality of chip regions; and a rescue circuit configured to disable a failed plane and enable a normal plane from among the plurality of planes, wherein the semiconductor memory device operates with only normal planes that are enabled.

Abstract: A memory device includes a memory cell array included in a first semiconductor layer, and including a plurality of row lines that extend in a first direction, each of the plurality of row lines having a pad part disposed in a slimming region; a row decoder included in a second semiconductor layer disposed under the first semiconductor layer, and overlapping the memory cell array in a vertical direction; slimming regions disposed on both sides of the row decoder in the first direction; and a plurality of wiring lines coupling the pad parts of the plurality of row lines and the row decoder.

Abstract: A semiconductor memory device includes a first semiconductor layer including a memory cell array; a second semiconductor layer including a first substrate and a page buffer circuit which is configured on the first substrate; a third semiconductor layer disposed between the first semiconductor layer and the second semiconductor layer in a vertical direction, and including a second substrate and a second logic circuit which is configured on an element region of the second substrate; and a first contact plug passing through a coupling region of the second substrate which overlaps the page buffer circuit in the vertical direction.

Abstract: A semiconductor device includes a lower wafer including a first substrate, a first dielectric layer that is defined on the first substrate, and a first wiring line that is defined in the first dielectric layer; an upper wafer including a second substrate, an isolation layer that is defined in an upper surface of the second substrate, a second dielectric layer, bonded to an upper surface of the first dielectric layer, that covers a lower surface of the second substrate and that includes at least one portion defined in the lower surface of the second substrate below and in contact with the isolation layer, and a third dielectric layer that is defined on the upper surface of the second substrate, and a second wiring line that is defined on the third dielectric layer; and a through via passing through, under the second wiring line, the third dielectric layer, the isolation layer, the second dielectric layer under the isolation layer and the first dielectric layer, and coupling the second wiring line and the first

Abstract: A semiconductor memory device includes a memory structure including a plurality of memory cells which are disposed on a cell region of a source plate; a plurality of contact plugs passing through the source plate in a coupling region of the source plate including at least a portion of a center portion of the source plate, and separated from the source plate by a dielectric layer pattern; a discharge contact passing through the source plate in the coupling region, and coupled to the center portion of the source plate; and a discharge region coupled to the discharge contact. The discharge region is located in a substrate below the source plate.

Abstract: A semiconductor device is disclosed, which relates to a three-dimensional (3D) semiconductor memory device. The semiconductor device includes a first connection pattern, a bit line disposed over the first connection pattern in a vertical direction, and a bit-line contact pad, disposed in a first layer between the bit line and the first connection pattern to electrically couple the bit line to the first connection pattern so that the bit-line contact pad, and formed as an island when viewed along the vertical direction.

Abstract: A three-dimensional memory device and a manufacturing method thereof. The three-dimensional memory device includes an electrode structure including a plurality of electrode layers and a plurality of interlayer dielectric layers which are alternately stacked on a substrate; and a plurality of through holes passing through the electrode structure in a vertical direction, and including pad regions at the transition between portions of the through holes have different widths.

Abstract: A semiconductor device having a three-dimensional structure includes a first wafer including a first bonding pad on one surface thereof; a second wafer including a second bonding pad, which is bonded to the first bonding pad, on one surface thereof bonded to the one surface of the first wafer; a plurality of anti-warpage grooves on the one surface of the first wafer, and laid out in a stripe shape; and a plurality of anti-warpage ribs on the one surface of the second wafer and coupled respectively to the plurality of anti-warpage grooves, and laid out in a stripe shape.

Abstract: A memory device includes a plurality of bit lines extending in a first direction and arranged in a second direction; and a cell region including a plane which is coupled to the plurality of bit lines, wherein the plane is divided into a plurality of memory groups each including a plurality of partial pages to be disposed in a plurality of rows in the first direction.

Abstract: A memory may include a first wafer, and a second wafer stacked on and bonded to the first wafer. The first wafer may include a cell structure including a memory cell array; and a first logic structure disposed under the cell structure, and including a row control circuit. The second wafer may include a second logic structure including a column control circuit.

Abstract: A memory device includes a pass transistor circuit included in a first wafer, and configured to transfer an operating voltage to row lines of a memory cell array; and a discharge transistor circuit included in a second wafer that overlaps with the first wafer in a vertical direction, and configured to transfer a discharge voltage to at least one of the row lines.

Abstract: A three-dimensional memory device includes an electrode structure including a plurality of electrode layers and a plurality of interlayer dielectric layers which are alternately stacked on a substrate; a first stairway structure and a second stairway structure defined in the electrode structure, and positioned at different heights from each other; a sidewall of the electrode structure formed due to a difference in height between the first stairway structure and the second stairway structure; and a dielectric support passing through the electrode structure, and isolating a corner portion of the sidewall from the plurality of electrode layers.

Abstract: A semiconductor memory device includes a stacked structure including a plurality of conductive layers and a plurality of interlayer insulating layers, which are alternately stacked on a substrate; stepped grooves provided in the stacked structure, the stepped grooves having different depths from each other; and an opening portion penetrating the stacked structure to contact the substrate and having steps on sidewalls, the steps having heights corresponding to depth differences between stepped grooves.

Abstract: A memory device is disclosed. The disclosed memory device may include a first wafer, and a second wafer stacked on and bonded to the first wafer. The first wafer may include a cell structure including a memory cell array; and a first logic structure disposed under the cell structure, and including a column control circuit. The second wafer may include a second logic structure including a row control circuit.

Abstract: A semiconductor memory device includes an electrode structure including a plurality of electrode layers and a plurality of interlayer dielectric layers which are alternately stacked on a source plate defined with a cell area and a connection area in a first direction; a vertical channel passing through the electrode structure in the cell area; a hard mask pattern disposed on the electrode structure in the connection area, and having a plurality of opening holes; a plurality of contact holes defined in the electrode structure under the opening holes, and exposing pad areas of the electrode layers; and a slit dividing the hard mask pattern into units smaller than the electrode structure in the connection area.

Abstract: A three-dimensional memory device includes an electrode structure including a plurality of interlayer dielectric layers and a plurality of electrode layers which are alternately stacked on a first substrate, each of the plurality of electrode layers having a pad part which does not overlap with another electrode layer positioned on the electrode layer; a pass transistor positioned below the first substrate; and a first contact passing through the electrode structure from the pad part of one of the plurality of electrode layers, and coupling the pad part and the pass transistor.