Abstract: A semiconductor memory device includes a latch defined on a circuit chip; and a bit line select transistor defined in a first memory chip stacked in the circuit chip and a second memory chip stacked on the first memory chip. The bit line select transistors exchange data with the latch.

Abstract: A semiconductor memory device includes at least two transistors, each including a gate that traverses, in a first direction, an active region of a first substrate defined by an isolation layer, and junction regions disposed in the active region on opposite sides of the gate, and coupled to a memory cell array through a bit line; and a plurality of contacts, coupled respectively to the junction regions, that pass through a dielectric layer that covers the transistor. Among the plurality of contacts, a contact coupled to a junction region to which an erase voltage is loaded is disposed at a center portion of the active region in the first direction, and a contact coupled to a junction region to which the erase voltage is not loaded is disposed at an edge portion of the active region in the first direction.

Abstract: A semiconductor memory device includes a stack structure including a plurality of first dielectric layers alternately stacked with a plurality of second dielectric layers over a first substrate in a coupling region, and including a plurality of electrode layers alternately stacked with the plurality of first dielectric layers over the first substrate outside the coupling region; and a plurality of vias passing through the stack structure in a first direction that is perpendicular to a top surface of the first substrate and disposed at edges of the coupling region to define an etch barrier. Each of the plurality of vias comprising: a pillar portion extending in the first direction; and a plurality of extended portions, extending radially from an outer circumference of the pillar portion and parallel to the top surface of the first substrate, that are coextensive in the first direction with the plurality of second dielectric layers.

Abstract: A semiconductor memory device includes a plurality of page buffers defined in active regions of a substrate; and a plurality of wiring lines disposed over the page buffers, and coupled to the page buffers through contacts. The plurality of wiring lines may include contact portions which are coupled with the contacts, respectively. The plurality of wiring lines may be configured into a bent shape such that the contact portions are offset toward center lines of the active regions.

Abstract: A semiconductor memory device includes a stacked structure including a plurality of conductive layers and a plurality of interlayer insulating layers, which are alternately stacked on a substrate; stepped grooves provided in the stacked structure, the stepped grooves having different depths from each other; and an opening portion penetrating the stacked structure to contact the substrate and having steps on sidewalls, the steps having heights corresponding to depth differences between stepped grooves.

Abstract: A semiconductor memory device includes an electrode structure including a plurality of electrode layers and a plurality of interlayer dielectric layers which are alternately stacked on a source plate defined with a cell area and a connection area in a first direction; a vertical channel passing through the electrode structure in the cell area; a hard mask pattern disposed on the electrode structure in the connection area, and having a plurality of opening holes; a plurality of contact holes defined in the electrode structure under the opening holes, and exposing pad areas of the electrode layers; and a slit dividing the hard mask pattern into units smaller than the electrode structure in the connection area.

Abstract: A method for manufacturing a semiconductor memory device may include: forming a pre-stack by alternately stacking a plurality of first dielectric layers and a plurality of second dielectric layers over a substrate which has a cell area and a connection area; forming a plurality of slits which pass through the pre-stack, such that a distance between the slits in the connection area is larger than a distance between the slits in the cell area; removing the second dielectric layers in the cell area and in a periphery of the connection area adjacent to the slits while leaving the second dielectric layer in a center of the connection area by injecting an etching solution for removing the second dielectric layers, through the slits; and forming electrode layers in spaces from which the second dielectric layers are removed.

Abstract: A semiconductor device includes an internal circuit and a power mesh configured to transmit an operating voltage to the internal circuit. The power mesh includes first power lines extending in a first direction and arranged in a second direction intersecting with the first direction, when viewed from a top; second power lines sharing lanes with the first power lines and at least partially overlapping with the first power lines in the second direction; first power straps extending in the second direction and coupled to the first power lines; and second power straps extending in the second direction and coupled to the second power lines. Each of the first and second power lines may have a width of the same size as a width of each lane in sections where they do not overlap, and may have a width of a size smaller than the width of each lane in sections where they overlap.

Abstract: A semiconductor memory device includes a cell wafer including a first plane and a second plane which are disposed to be adjacent to each other in a first direction and each include a plurality of memory cells; and a peripheral wafer including a row decoder which simultaneously controls the first and second planes and first and second page buffer circuits which control the first and second planes, respectively. The cell wafer includes, on one surface thereof bonded to the peripheral wafer, a first pad which is coupled in common with the first plane and the second plane, and the peripheral wafer includes, on one surface thereof bonded to the cell wafer, a second pad which is coupled with the row decoder and is bonded to the first pad.

Abstract: A semiconductor device includes a first chip, divided into a plurality of regions, including a plurality of first pads and a plurality of first test pads in each of the plurality of regions; and a second chip including a plurality of second pads corresponding to the plurality of first pads and a plurality of second test pads corresponding to the plurality of first test pads, and bonded onto the first chip such that the plurality of second pads are coupled to the plurality of first pads. The second chip includes a voltage generation circuit linked to the plurality of second pads, that provides a compensated voltage to the plurality of second pads for each of the plurality of regions, based on a voltage drop value for each region due to a contact resistance between the plurality of first test pads and the plurality of second test pads.

Abstract: A semiconductor memory device includes a memory cell array; a page buffer circuit including a plurality of page buffers which are coupled to the memory cell array through a plurality of bit lines which extend in a second direction intersecting with a first direction; and a cache latch circuit including a plurality of cache latches which are coupled to the plurality of page buffers. The plurality of cache latches have a two-dimensional arrangement in the first direction and the second direction. Among the plurality of cache latches, an even cache latch and an odd cache latch which share a data line and an inverted data line are disposed adjacent to each other in the first direction.

Abstract: A semiconductor memory device includes a stack disposed over a first substrate; an etch barrier including a plurality of dummy channels which pass through the stack and surround a coupling region; and a plurality of channels passing through the stack in a cell region outside the coupling region. The stack has a structure in which first dielectric layers and second dielectric layers are alternately stacked, inside the coupling region, and has a structure in which the first dielectric layers and electrode layers are alternately stacked, outside the coupling region.

Abstract: A semiconductor memory device includes an electrode structure including a plurality of electrode layers and a plurality of interlayer dielectric layers which are alternately stacked on a source plate defined with a cell area and a connection area in a first direction; a vertical channel passing through the electrode structure in the cell area; a hard mask pattern disposed on the electrode structure in the connection area, and having a plurality of opening holes; a plurality of contact holes defined in the electrode structure under the opening holes, and exposing pad areas of the electrode layers; and a slit dividing the hard mask pattern into units smaller than the electrode structure in the connection area.

Abstract: Disclosed is a semiconductor memory device. The semiconductor memory device may include: a memory cell array; and a cache latch circuit configured to exchange data with the memory cell array through a plurality of bit lines extended in a second direction crossing a first direction, and comprising a plurality of cache latches arranged in a plurality of column in the first direction and in a plurality of rows in the second direction. Each of the cache latches may be coupled to any one of a plurality of input/output (IO) pins. Cache latches coupled to the IO pins at the same time may constitute one IO cache latch unit. The cache latches included in the one IO cache latch unit may be arranged in 2×2 array units.

Abstract: A semiconductor memory device includes: a plurality of page buffers disposed on a substrate; and a plurality of pads exposed to one surface of a dielectric layer covering the page buffers, and coupled to the respective page buffers. The substrate comprises a plurality of high voltage regions and a plurality of low voltage regions which are alternately disposed in a second direction crossing a first direction. Each of the plurality of page buffers comprises a sensing unit and a bit line select transistor coupled between the sensing unit and the one of the plurality of pads. The bit line select transistors of the plurality of page buffers are disposed in the plurality of high voltage regions, and the plurality of pads are distributed and disposed in a plurality of pad regions which correspond to the high voltage regions and are spaced apart from each other in the second direction.

Abstract: A semiconductor memory device includes a substrate defined with a cell array region and a connection region which extends in a first direction from the cell array region; an electrode structure including a bottom electrode structure which includes plurality of bottom electrodes stacked on the substrate to be separated from one another and a top electrode structure which includes plurality of top electrodes stacked on the bottom electrode structure to be separated from one another and has a stepped structure which includes plurality of stepping surfaces, in the connection region; and plurality of recess holes formed to a first depth from stepping surfaces of the stepped structure, and having bottom surfaces which expose the bottom electrode structure, wherein the first depth is substantially same as a height of the top electrode structure, and distances of the bottom surfaces of the recess holes from the substrate are different from one another.

Abstract: A semiconductor memory device includes an electrode structure including a plurality of electrode layers and a plurality of interlayer dielectric layers which are alternately stacked on a source plate defined with a cell area and a connection area in a first direction; a vertical channel passing through the electrode structure in the cell area; a hard mask pattern disposed on the electrode structure in the connection area, and having a plurality of opening holes; a plurality of contact holes defined in the electrode structure under the opening holes, and exposing pad areas of the electrode layers; and a slit dividing the hard mask pattern into units smaller than the electrode structure in the connection area.

Abstract: A semiconductor memory device includes an electrode structure including a plurality of electrode layers and a plurality of interlayer dielectric layers which are alternately stacked on a substrate defined with a plurality of cell areas and a plurality of coupling areas in a first direction; a hard mask pattern disposed on the electrode structure, and having a plurality of opening holes in the coupling areas; and a plurality of contact holes defined in the electrode structure under the plurality of opening holes, and exposing pad areas of the electrode layers, respectively. The plurality of opening holes are disposed by being distributed in a plurality of rows arranged in a second direction intersecting with the first direction.

Abstract: A semiconductor memory device includes a stack disposed over a substrate defined with cell and connection areas; channel structures passing through the stack in the cell area; and slits defined in the stack. The stack includes first dielectric layers separately staked in the cell and connection areas; electrode layers disposed alternately with the first dielectric layers in the cell area and a periphery of the connection area adjacent to the slits; and second dielectric layers disposed alternately with the first dielectric layers in a central part of the connection area distant from the slits. A distance between the slits in the connection area is larger than a distance between the slits in the cell area, and, at a boundary between the periphery and the central part of the connection area, the electrode layers and the second dielectric layers disposed at the same layers are in contact with each other.

Abstract: A semiconductor memory device includes a stack disposed over a substrate defined with cell and connection areas; channel structures passing through the stack in the cell area; and slits defined in the stack. The stack includes first dielectric layers separately staked in the cell and connection areas; electrode layers disposed alternately with the first dielectric layers in the cell area and a periphery of the connection area adjacent to the slits; and second dielectric layers disposed alternately with the first dielectric layers in a central part of the connection area distant from the slits. A distance between the slits in the connection area is larger than a distance between the slits in the cell area, and, at a boundary between the periphery and the central part of the connection area, the electrode layers and the second dielectric layers disposed at the same layers are in contact with each other.