Abstract: A semiconductor memory device includes a plurality of memory cell arrays accessed through a plurality of row lines and a plurality of bit lines; a pass transistor coupled to one of the plurality of row lines and configured to transfer an operating voltage to the one of the plurality of row lines; and a plurality of wiring lines disposed in a wiring line layer over the pass transistor. The wiring line layer includes a wiring inhibition interval which overlaps a source and a drain of the pass transistor. One or more of the plurality of wiring lines is disposed outside of the wiring inhibition interval.

Abstract: A semiconductor memory device includes a memory cell array; and a page buffer circuit coupled to the memory cell array through a plurality of bit lines which extend in a second direction intersecting with a first direction. The page buffer circuit includes a plurality of bit line select transistors coupled to the plurality of bit lines; a plurality of latches coupled to the plurality of bit line select transistors, respectively; and a plurality of erase bias pass transistors coupled to the plurality of bit lines, and configured to transfer an erase voltage to the bit lines. The plurality of erase bias pass transistors and the plurality of bit line select transistors are disposed in different regions, and are not adjacent to each other.

Abstract: A semiconductor memory device includes a substrate having a second region extending in a first direction; a memory block including electrodes; a slit dividing the memory block into first and second electrode structures in the second region; and step-shaped grooves formed in the memory block in the second region, and divided by the slit. In the second region, the first and second electrode structures are adjacently disposed with the slit interposed therebetween, in a second direction intersecting with the first direction. Each of the electrodes of the first electrode structure has a first pad region, each of the electrodes of the second electrode structure has a second pad region, and first and second pad regions of the first and second electrode structures which are positioned in the same step-shaped groove and are disposed at the same layers are adjacently disposed in the second direction with the slit interposed therebetween.

Abstract: A memory device includes a plurality of bit lines extending in a first direction and arranged in a second direction perpendicular to the first direction; a page buffer circuit including a plurality of page buffers which are electrically coupled to the plurality of bit lines; and a cache circuit including a plurality of caches which are electrically coupled to the plurality of page buffers, wherein the page buffer circuit is divided into a plurality of page buffer regions and is laid out at both sides of the cache circuit in the first direction.

Abstract: A semiconductor memory device includes a plurality of bit lines electrically coupled to a memory cell array and extending in a first direction; bit line contact pads formed on a first plane over a substrate and respectively coupled to the bit lines through bit line contacts; and first contact pads formed on the first plane, respectively coupled to the bit line contact pads through redistribution lines, and electrically coupled to a page buffer circuit which is disposed on the substrate, through first contacts, wherein at least two first contact pads corresponding to at least two bit line contact pads which are disposed in a line in a second direction crossing with the first direction are disposed in a line in the first direction.

Abstract: A semiconductor device includes an internal circuit and a power mesh configured to transmit an operating voltage to the internal circuit. The power mesh includes first power lines extending in a first direction and arranged in a second direction intersecting with the first direction, when viewed from a top; second power lines sharing lanes with the first power lines and at least partially overlapping with the first power lines in the second direction; first power straps extending in the second direction and coupled to the first power lines; and second power straps extending in the second direction and coupled to the second power lines. Each of the first and second power lines may have a width of the same size as a width of each lane in sections where they do not overlap, and may have a width of a size smaller than the width of each lane in sections where they overlap.

Abstract: A semiconductor memory device includes a substrate defined with a cell array region and a connection region which extends in a first direction from the cell array region; an electrode structure including a bottom electrode structure which includes plurality of bottom electrodes stacked on the substrate to be separated from one another and a top electrode structure which includes plurality of top electrodes stacked on the bottom electrode structure to be separated from one another and has a stepped structure which includes plurality of stepping surfaces, in the connection region; and plurality of recess holes formed to a first depth from stepping surfaces of the stepped structure, and having bottom surfaces which expose the bottom electrode structure, wherein the first depth is substantially same as a height of the top electrode structure, and distances of the bottom surfaces of the recess holes from the substrate are different from one another.

Abstract: A semiconductor memory device includes a cell wafer including a first plane and a second plane which are disposed to be adjacent to each other in a first direction and each include a plurality of memory cells; and a peripheral wafer including a row decoder which simultaneously controls the first and second planes and first and second page buffer circuits which control the first and second planes, respectively. The cell wafer includes, on one surface thereof bonded to the peripheral wafer, a first pad which is coupled in common with the first plane and the second plane, and the peripheral wafer includes, on one surface thereof bonded to the cell wafer, a second pad which is coupled with the row decoder and is bonded to the first pad.

Abstract: A semiconductor memory device includes gate lines and wiring lines which are stacked over a substrate. The gate lines are stacked over first and second cell array regions of a substrate which are disposed in a second direction crossing with a first direction, and are passed through by channel structures. The wiring lines are stacked over an interval region of the substrate which is disposed between the first and second cell array regions and over first coupling regions of the substrate which are disposed at both sides of the first and second cell array regions and the interval region in the first direction. Each of the wiring lines includes a line portion which traverses the interval region in the first direction and extended portions which are disposed over the first coupling regions. A width of the extended portions is larger than a width of the line portion.

Abstract: A semiconductor memory device comprises a memory cell array disposed on a substrate, a plurality of bit lines disposed on the a memory cell array, each bit line extending in a first direction parallel to the top surface of the substrate and divided into a first bit line section and a second bit line section, and a plurality of source line pads disposed at the same layer as the bit lines between the first bit line sections of the bit lines and the second bit line sections of the bit lines.

Abstract: A memory device includes a plurality of bit lines; a page buffer circuit including a plurality of page buffers which are electrically coupled to the plurality of bit lines; and a cache circuit including a plurality of caches which are electrically coupled to the plurality of page buffers, wherein a number of stages of the page buffer circuit is less than a number of stages of the cache circuit.

Abstract: A semiconductor memory device includes a stacked structure including a plurality of conductive layers and a plurality of interlayer insulating layers, which are alternately stacked on a substrate; stepped grooves provided in the stacked structure, the stepped grooves having different depths from each other; and an opening portion penetrating the stacked structure to contact the substrate and having steps on sidewalls, the steps having heights corresponding to depth differences between stepped grooves.

Abstract: A semiconductor memory device includes a memory chip defined with a first pad on one surface thereof; and a circuit chip defined with a second pad which is coupled with the first pad, on one surface thereof bonded with the one surface of the memory chip. The memory chip comprising: a memory cell array; a bit line disposed in a first wiring layer between the one surface and the memory cell array, and separated into a first bit line section and a second bit line section; and a power pad disposed in a space between the first bit line section and the second bit line section in the first wiring layer, and coupled with the first pad.

Abstract: A semiconductor memory device includes a memory structural body including first and second planes each of which includes memory cells coupled to word lines extending in a first direction and bit lines extending in a second direction and which are disposed along the first direction; and a logic structural body disposed between a substrate and the memory structural body, and including a row decoder. The row decoder includes a pass transistor circuit which is coupled in common to the first and second planes and a block switch circuit which controls the pass transistor circuit. The block switch circuit is disposed in first and second plane regions of the logic structural body which overlap with the first and second planes in a third direction perpendicular to the first and second directions, and the pass transistor circuit is disposed in an interval region between the first and second plane regions.

Abstract: A semiconductor memory device with a three-dimensional (3D) structure may include: a cell region arranged over a substrate, including a cell structure; a peripheral circuit region arranged between the substrate and the cell region; an upper wiring structure arranged over the cell region; main channel films and dummy channel films formed through the cell structure. The dummy channel films are suitable for electrically coupling the upper wiring structure.

Abstract: A semiconductor memory device includes a substrate defined with a first cell region, a slimming region extending from the first cell region in a first direction and a second cell region extending from the slimming region in the first direction; first and second electrode structures each including electrodes which are stacked on the substrate, and disposed to be separated from each other in a second direction crossing with the first direction, with a slit interposed therebetween; and a plurality of step-shaped holes disposed in the slimming region along the first direction, and respectively formed in the first and second electrode structures. Each of the step-shaped holes includes first step structures which face each other in the first direction, are symmetrical to each other and are separated by the slit and second step structures which face each other in the second direction and are symmetrical to each other.

Abstract: A semiconductor memory device includes a plurality of bit lines electrically coupled to a memory cell array and extending in a first direction; bit line contact pads formed on a first plane over a substrate and respectively coupled to the bit lines through bit line contacts; and first contact pads formed on the first plane, respectively coupled to the bit line contact pads through redistribution lines, and electrically coupled to a page buffer circuit which is disposed on the substrate, through first contacts, wherein at least two first contact pads corresponding to at least two bit line contact pads which are disposed in a line in a second direction crossing with the first direction are disposed in a line in the first direction.

Abstract: A semiconductor memory device includes a plurality of pass transistors disposed along a first direction over a substrate, and configured to transfer operating voltages to a memory cell array; and a plurality of global lines formed in a first wire layer over the pass transistors, extending in a second direction intersecting with the first direction, and configured to transfer the operating voltages to the corresponding pass transistors respectively. The global lines are disposed in first direction pitches of some pass transistors among the pass transistors.

Abstract: A semiconductor memory device includes a logic structure including a peripheral circuit element which is formed over a substrate, a bottom dielectric layer which covers the peripheral circuit element and a bottom wiring line which is disposed in the bottom dielectric layer and is coupled to the peripheral circuit element; a memory structure stacked over the logic structure in a first direction perpendicular to a top surface of the substrate; a bit line disposed over a first top dielectric layer which covers the memory structure, extending in a second direction parallel to the top surface of the substrate, and divided into first and second bit line sections; and a power pad disposed over the first top dielectric layer between the first bit line section and the second bit line section, and coupled to the bottom wiring line through a power coupling contact which passes through the memory structure.

Abstract: A semiconductor memory device includes gate lines and wiring lines which are stacked over a substrate. The gate lines are stacked over first and second cell array regions of a substrate which are disposed in a second direction crossing with a first direction, and are passed through by channel structures. The wiring lines are stacked over an interval region of the substrate which is disposed between the first and second cell array regions and over first coupling regions of the substrate which are disposed at both sides of the first and second cell array regions and the interval region in the first direction. Each of the wiring lines includes a line portion which traverses the interval region in the first direction and extended portions which are disposed over the first coupling regions. A width of the extended portions is larger than a width of the line portion.