Abstract: A semiconductor memory device mc des a substrate defined with cell regions and a contact region between the cell regions; a dielectric structure formed over the contact region; a memory block having cell parts which are respectively formed over the cell regions, a coupling part which is formed over the contact region and couples the cell parts, and a through part which accommodates the dielectric structure; a peripheral circuit formed over the substrate under the memory block; bottom wiring lines disposed between the memory block and the peripheral circuit, and electrically coupled with the peripheral circuit; top wiring lines disposed over the memory block; and contact plugs passing through the dielectric structure and coupling the bottom wiring lines and the top wiring lines.

Abstract: A semiconductor memory device with a three-dimensional (3D) structure may include: a cell region arranged over a substrate, including a cell structure; a peripheral circuit region arranged between the substrate and the cell region; an upper wiring structure arranged over the cell region; main channel films and dummy channel films formed through the cell structure. The dummy channel films are suitable for electrically coupling the upper wiring structure.

Abstract: A memory device includes a plurality of bit lines extending in a first direction and arranged in a second direction perpendicular to the first direction; a page buffer circuit including a plurality of page buffers which are electrically coupled to the plurality of bit lines; and a cache circuit including a plurality of caches which are electrically coupled to the plurality of page buffers, wherein the page buffer circuit is divided into a plurality of page buffer regions and is laid out at both sides of the cache circuit in the first direction.

Abstract: A semiconductor memory device includes a substrate defined with a first cell region, a slimming region extending from the first cell region in a first direction and a second cell region extending from the slimming region in the first direction; first and second electrode structures each including electrodes which are stacked on the substrate, and disposed to be separated from each other in a second direction crossing with the first direction, with a slit interposed therebetween; and a plurality of step-shaped holes disposed in the slimming region along the first direction, and respectively formed in the first and second electrode structures. Each of the step-shaped holes includes first step structures which face each other in the first direction, are symmetrical to each other and are separated by the slit and second step structures which face each other in the second direction and are symmetrical to each other.

Abstract: A memory device includes a plurality of bit lines; a page buffer circuit including a plurality of page buffers which are electrically coupled to the plurality of bit lines; and a cache circuit including a plurality of caches which are electrically coupled to the plurality of page buffers, wherein a number of stages of the page buffer circuit is less than a number of stages of the cache circuit.

Abstract: A semiconductor memory device includes a memory structural body including first and second planes each of which includes memory cells coupled to word lines extending in a first direction and bit lines extending in a second direction and which are disposed along the first direction; and a logic structural body disposed between a substrate and the memory structural body, and including a row decoder. The row decoder includes a pass transistor circuit which is coupled in common to the first and second planes and a block switch circuit which controls the pass transistor circuit. The block switch circuit is disposed in first and second plane regions of the logic structural body which overlap with the first and second planes in a third direction perpendicular to the first and second directions, and the pass transistor circuit is disposed in an interval region between the first and second plane regions.

Abstract: A semiconductor memory device includes first and second memory blocks each including conductive and dielectric layers alternately stacked over a semiconductor layer disposed over a substrate, and disposed adjacent to each other in a first direction; a dummy block disposed over the semiconductor layer, and provided between the first and second memory blocks; first pass transistors formed over the substrate below the first memory block, and coupled to conductive layers, respectively, of the first memory block; second pass transistors formed over the substrate below the second memory block, and coupled to conductive layers, respectively, of the second memory block; bottom global row lines between the first and second pass transistors and the semiconductor layer, and each coupled to one of the first pass transistors and one of the second pass transistors; and top global row lines formed over the dummy block, and coupled to the bottom global row lines.

Abstract: A semiconductor memory device includes a plurality of pass transistors disposed along a first direction over a substrate, and configured to transfer operating voltages to a memory cell array; and a plurality of global lines formed in a first wire layer over the pass transistors, extending in a second direction intersecting with the first direction, and configured to transfer the operating voltages to the corresponding pass transistors respectively. The global lines are disposed in first direction pitches of some pass transistors among the pass transistors.

Abstract: A memory device includes a substrate, channel structures disposed over the substrate and extending in a first direction perpendicular to a top surface of the substrate, a plurality of gate lines surrounding the channel structures and stacked over the substrate along the first direction, and a wiring line disposed at the same layer as at least one of the gate lines.

Abstract: A semiconductor memory device comprises a memory cell array disposed on a substrate, a plurality of bit lines disposed on the a memory cell array, each bit line extending in a first direction parallel to the top surface of the substrate and divided into a first bit line section and a second bit line section, and a plurality of source line pads disposed at the same layer as the bit lines between the first bit line sections of the bit lines and the second bit line sections of the bit lines.

Abstract: A memory device includes a memory cell array; bit lines including even and odd bit lines extending in a first direction and alternately disposed; cache latches including even cache latches which exchange data with the memory cell array through the even bit lines and odd cache latches which exchange data with the memory cell array through the odd bit lines; 2^k data lines, where k is a natural number equal to or greater than 2, respectively corresponding to 2^k input/output pins; and column merge units respectively allocated to the input/output pins, and each suitable for coupling any one of the even cache latches or any one of the odd cache latches to a data line corresponding to an input/output pin to which it is allocated. A pitch of the column merge units in a second direction intersecting the first direction is greater than a pitch of the cache latches.

Abstract: A semiconductor memory device includes a logic structure including a peripheral circuit element which is formed over a substrate, a bottom dielectric layer which covers the peripheral circuit element and a bottom wiring line which is disposed in the bottom dielectric layer and is coupled to the peripheral circuit element; a memory structure stacked over the logic structure in a first direction perpendicular to a top surface of the substrate; a bit line disposed over a first top dielectric layer which covers the memory structure, extending in a second direction parallel to the top surface of the substrate, and divided into first and second bit line sections; and a power pad disposed over the first top dielectric layer between the first bit line section and the second bit line section, and coupled to the bottom wiring line through a power coupling contact which passes through the memory structure.

Abstract: A memory device includes a substrate, channel structures disposed over the substrate and extending in a first direction perpendicular to a top surface of the substrate, a plurality of gate lines surrounding the channel structures and stacked over the substrate along the first direction, and a wiring line disposed at the same layer as at least one of the gate lines.

Abstract: A semiconductor memory device includes first and second memory blocks each including conductive and dielectric layers alternately stacked over a semiconductor layer disposed over a substrate, and disposed adjacent to each other in a first direction; a dummy block disposed over the semiconductor layer, and provided between the first and second memory blocks; first pass transistors formed over the substrate below the first memory block, and coupled to conductive layers, respectively, of the first memory block; second pass transistors formed over the substrate below the second memory block, and coupled to conductive layers, respectively, of the second memory block; bottom global row lines between the first and second pass transistors and the semiconductor layer, and each coupled to one of the first pass transistors and one of the second pass transistors; and top global row lines formed over the dummy block, and coupled to the bottom global row lines.

Abstract: A memory device includes a memory cell array; bit lines including even and odd bit lines extending in a first direction and alternately disposed; cache latches including even cache latches which exchange data with the memory cell array through the even bit lines and odd cache latches which exchange data with the memory cell array through the odd bit lines; 2?k data lines, where k is a natural number equal to or greater than 2, respectively corresponding to 2?k input/output pins; and column merge units respectively allocated to the input/output pins, and each suitable for coupling any one of the even cache latches or any one of the odd cache latches to a data line corresponding to an input/output pin to which it is allocated. A pitch of the column merge units in a second direction intersecting the first direction is greater than a pitch of the cache latches.

Abstract: A semiconductor memory device includes a peripheral circuit element provided over a lower substrate; an upper substrate provided over an interlayer dielectric layer which partially covers the peripheral circuit element; a memory cell array including a channel structure which extends in a first direction perpendicular to a top surface of the upper substrate and a plurality of gate lines which are stacked over the upper substrate to surround the channel structure; and a plurality of transistors electrically coupling the gate lines to the peripheral circuit element. The transistors include a gate electrode provided over the interlayer dielectric layer and disposed to overlap with the memory cell array in the first direction; a plurality of vertical channels passing through the gate electrode in the first direction and electrically coupled to the gate lines, respectively; and gate dielectric layers disposed between the vertical channels and the gate electrode.

Abstract: A nonvolatile memory device includes bit lines arranged in a first direction over a substrate; a memory cell array disposed between the substrate and the bit lines, and including a plurality of planes which are arranged in a second direction perpendicular to the first direction; page buffer circuits disposed between the substrate and the memory cell array; contact pads disposed between the substrate and the memory cell array, the contact pads being suitable for electrically coupling the bit lines and the page buffer circuits; and routing lines disposed at the same layer as the contact pads, and extending in the second direction, wherein the contact pads are disposed to overlap with at least two lines which are arranged in the second direction, and the routing lines are formed in a bent pattern to pass between the contact pads which are disposed to overlap with different lines.

Abstract: A nonvolatile memory device includes bit lines arranged in a first direction over a substrate; a memory cell array disposed between the substrate and the bit lines, and including a plurality of planes which are arranged in a second direction perpendicular to the first direction; page buffer circuits disposed between the substrate and the memory cell array; contact pads disposed between the substrate and the memory cell array, the contact pads being suitable for electrically coupling the bit lines and the page buffer circuits; and routing lines disposed at the same layer as the contact pads, and extending in the second direction, wherein the contact pads are disposed to overlap with at least two lines which are arranged in the second direction, and the routing lines are formed in a bent pattern to pass between the contact pads which are disposed to overlap with different lines.

Abstract: A nonvolatile memory device includes well regions formed in a substrate and arranged in a first direction; a memory block including sub blocks which are formed over the substrate and correspond to the well regions, respectively; and bit lines disposed over the memory block, and extending in the first direction. Each of the sub blocks includes channel layers which are formed in a vertical direction between a corresponding well region and the bit lines, word lines and at least one drain select line and at least one erase prevention line, which are stacked over the substrate along the channel layers. In an erase operation, an erase voltage is applied to a well region corresponding to a selected sub block and an erase preventing voltage is applied to an erase prevention line included in an unselected sub block, the erase voltage may be prevented from being transferred to the unselected sub block.

Abstract: A memory device includes a memory cell array, a plurality of bit lines, and a plurality of page buffers including a plurality of cache latches, exchanging data with the memory cell array through the plurality of bit lines, wherein the plurality of cache latches are arranged in a column direction in parallel with the plurality of bit lines and a row direction perpendicular to the plurality of bit lines, and have a two-dimensional arrangement of M stages in the column direction, where M is a positive integer not corresponding to 2L and L is zero or a natural number.