Abstract: A method for manufacturing a touch sensor panel with a reduced number of masks includes forming a first resist layer with both full and partial thickness patterns, the latter being at a region corresponding to a plurality of first sensor electrodes; etching a first transparent conductive layer and a first other conductive layer using the first resist layer patterns having both full and partial thicknesses; forming a second resist layer with both full and partial thickness patterns, the latter being at a region corresponding to a plurality of second sensor electrodes; and etching while using the second resist layer patterns.

Abstract: A liquid crystal display includes a substrate, a plurality of signal lines, a gate driver, and a sealant. The substrate includes a display area and a peripheral area outside the display area. The signal lines are integrated with the substrate and include a clock signal line. The gate driver includes a stage located between the clock signal line and the display area. The stage is integrated with the substrate and is configured to apply a gate voltage to the display area. The sealant is distributed over part of the peripheral area. A seal region where the sealant is distributed includes a seal line, and the clock signal line is located within the seal line. The clock signal line is located further away from the stage than the other signal lines.

Abstract: A liquid crystal display (LCD) includes a substrate; first and second pixel rows formed on the substrate and including a plurality of pixels; a first gate line extending in a row direction on the substrate and connected with the first pixel row; a second gate line extending in the row direction on the substrate, connected with the first pixel row; a third gate line extending in the row direction on the substrate, connected with the second pixel row, and adjacent to the second gate line; a fourth gate line extending in the row direction on the substrate, connected with the second pixel row; a plurality of data lines extending in a column direction on the substrate, wherein each of the data lines are disposed every two of the pixels; a first gate driver connected with the first and fourth gate lines and applying gate signals to the first and fourth gate lines; and a second gate driver connected with the second and third gate lines and applying gate signals to the second and third gate lines.

Abstract: A liquid crystal display includes pixels which is disposed in row and column directions, respectively includes pixel electrodes, and arranged along a first pixel column to a sixth pixel column, gate lines including pairs of two adjacent gate lines for each pixel row in the row direction, data lines including a first data line at a left side of the first pixel column, a second data line between the second and third pixel columns, a third data line between the fourth and fifth pixel columns, and a fourth data line at a right side of the sixth pixel column; and common voltage lines including a first common voltage line between the first and second pixel columns, a second common voltage line between the third and fourth pixel columns, and a third common voltage line between the fifth and sixth pixel columns.

Abstract: A gate drive circuit includes plural stages connected together one after each other. Each of the plural stages includes a circuit transistor, a capacitor part, a first connection part and a second connection part. The circuit transistor outputs the gate signal through a source electrode in response to a control signal applied through a gate electrode. The capacitor part includes a first electrode, a second electrode formed on the first electrode, and a third electrode formed on the second electrode. The first connection part electrically connects the gate electrode of the circuit transistor and the second electrode of the capacitor part. The second connection part electrically connects the source electrode of the circuit transistor and the first electrode of the capacitor part. Thus, an integrated size of a gate drive circuit may be decreased, and a reliability of a gate drive circuit may be enhanced.

Abstract: A thin film transistor array panel includes: a data line which extends in a column direction and transfers a data voltage; a first pixel electrode and a second pixel electrode connected to the data line and adjacent in a row direction; a first thin film transistor connected to the first pixel electrode and the data line, and including a first source electrode and a first drain electrode; and a second thin film transistor connected to the second pixel electrode and the data line, and including a second source electrode and a second drain electrode. The first pixel electrode is at the right of the data line, the second pixel electrode is at the left of the data line, and relative positions of the first source electrode and the first drain electrode are the same as relative positions of the second source electrode and the second drain electrode.

Abstract: In a thin film transistor array panel and a method of manufacturing the same, a thin passivation layer is positioned between a first field generating electrode and a second field generating electrode. The thin passivation layer overlaps the first and second field generating electrodes. The thin passivation layer includes a transparent photosensitive organic material. When forming the first field generating electrode, the passivation layer is used as a photosensitive film. Accordingly, the passivation layer and the first field generating electrode may be formed using a same single photo-mask. Accordingly, the manufacturing cost of the thin film transistor array panel may be reduced.

Abstract: A liquid crystal display includes a substrate, a plurality of signal lines, a gate driver, and a sealant. The substrate includes a display area and a peripheral area outside the display area. The signal lines are integrated with the substrate and include a clock signal line. The gate driver includes a stage located between the clock signal line and the display area. The stage is integrated with the substrate and is configured to apply a gate voltage to the display area. The sealant is distributed over part of the peripheral area. A seal region where the sealant is distributed includes a seal line, and the clock signal line is located within the seal line. The clock signal line is located further away from the stage than the other signal lines.

Abstract: A display substrate includes a gate line disposed on a base substrate and extending in a direction. A data line crosses the gate line. A thin film transistor comprises a gate electrode, a semiconductor pattern, a source electrode, and a drain electrode. The thin film transistor is connected to the gate line and the data line. A pixel electrode is connected to the thin film transistor. A light blocking pattern overlaps the semiconductor pattern. The light blocking pattern includes a haze-processed material of substantially the same material as the pixel electrode.

Abstract: A display apparatus includes a substrate and a display area and a peripheral area on the substrate. The peripheral area is outside the display area, and a gate driving circuit is disposed in the peripheral area. The gate driving circuit includes a first stage coupled to a first gate line and a second stage coupled to a second gate line, and the first stage and the second stage are configured as mirror images of each other.

Abstract: A liquid crystal display device includes a first substrate, a first electrode on the first substrate, and a second electrode on the first substrate, spaced apart from the first electrode and overlapping at least a part of the first electrode. the second electrode includes a plurality of branch electrodes, and a coupling portion which couples the plurality of branch electrodes to each other. The coupling portion includes a longitudinal coupling portion extended in a length direction of the branch electrode and a transverse coupling portion extended in a width direction of the branch electrode. An edge portion of the first electrode is disposed between at least one of the plurality of branch electrodes and the longitudinal coupling portion, in a plan view.

Abstract: A thin film transistor array panel includes: a data line which extends in a column direction and transfers a data voltage; a first pixel electrode and a second pixel electrode connected to the data line and adjacent in a row direction; a first thin film transistor connected to the first pixel electrode and the data line, and including a first source electrode and a first drain electrode; and a second thin film transistor connected to the second pixel electrode and the data line, and including a second source electrode and a second drain electrode. The first pixel electrode is at the right of the data line, the second pixel electrode is at the left of the data line, and relative positions of the first source electrode and the first drain electrode are the same as relative positions of the second source electrode and the second drain electrode.

Abstract: Provided is a gate driver including a plurality of stages respectively transferring gate-on voltages to a plurality of gate lines. The stage includes a pull-up driver including a first transistor, the first transistor having a control terminal connected to a first node, an output terminal connected to a output terminal of a present stage and an input terminal connected to a first clock terminal, a first node pull-down portion including a second transistor, the second transistor having an input terminal connected to a buffer node, an output terminal connected to the first node and a control terminal connected to a second node, and a buffer node stabilizer including a third transistor, the third transistor having an input terminal and a control terminal connected to the first node, and an output terminal connected to the buffer node.

Abstract: A liquid crystal display includes a first substrate, gate lines and data lines disposed on a display area of the first substrate, a common voltage line disposed on a peripheral area of the first substrate, a common voltage transmission unit extending from the common voltage line, an organic layer disposed on the common voltage transmission unit and the common voltage line, a connecting member disposed on the organic layer disposed on the peripheral area, a first insulating layer disposed on the pixel electrode and the connecting member, a common electrode disposed on the first insulating layer, and a short point connecting the connecting member and the common electrode to each other. The common electrode and the first insulating layer include a plurality of cutouts in the peripheral region and display region of the first substrate which have substantially a same plane shape as each other.

Abstract: A liquid crystal display according to an exemplary embodiment of the present disclosure includes: a gate line, a data line, and a compensation voltage line disposed on an insulation substrate; a first passivation layer disposed on the gate line, the data line, and the compensation voltage line; a pixel electrode connected to the gate line and the data line, and a compensation electrode connected to the compensation voltage line, disposed on the first passivation layer; and a common electrode formed on the first passivation layer, wherein the compensation electrode overlaps at least a portion of the data line, and the compensation voltage line is formed with the same layer as the data line.

Abstract: A liquid crystal display includes a first substrate, a plurality of signal lines on the first substrate, a first insulating layer positioned on the plurality of signal lines, a first electrode positioned on the first insulating layer, a second insulating layer positioned on the first electrode, a second electrode positioned on the second insulating layer, a second substrate facing the first substrate, a first spacer and a second spacer positioned between the first substrate and the second substrate, and a first cutout and a second cutout which are defined in the second electrode and the second insulating layer, respectively, and partially overlap the plurality of signal lines, where the second spacer overlaps the first cutout and the second cutout.

Abstract: A display substrate includes a gate line disposed on a base substrate and extending in a direction. A data line crosses the gate line. A thin film transistor comprises a gate electrode, a semiconductor pattern, a source electrode, and a drain electrode. The thin film transistor is connected to the gate line and the data line. A pixel electrode is connected to the thin film transistor. A light blocking pattern overlaps the semiconductor pattern. The light blocking pattern includes a haze-processed material of substantially the same material as the pixel electrode.

Abstract: A liquid crystal display device includes a first substrate, a thin film transistor on the first substrate, a first electrode on the first substrate and connected to the thin film transistor, a second substrate facing the first substrate, color filters on the first substrate or the second substrate, a black matrix between the color filters on the first substrate or the second substrate, a second electrode spaced apart from the first electrode and on the first substrate or the second substrate, a second electrode conductive line on the black matrix, a spacer which is between the first substrate and the second substrate and supports the first substrate and the second substrate, and a liquid crystal layer between the first substrate and the second substrate. The spacer is electrically connected to the second electrode and the second electrode conductive line.

Abstract: A display substrate includes a data line, a gate line and a fan-out line. The data line is disposed in a display area of a base substrate and transfers a data signal to a switching element electrically connected to a pixel electrode. The gate line is disposed in the display area and transfers a gate signal to the switching element. The fan-out line is disposed in a peripheral area of the base substrate surrounding the display area, electrically connected to at least one of the data line and the gate line, and includes a plurality of conductive layers making contact with each other through a contact hole.

Abstract: A liquid crystal display includes pixels which is disposed in row and column directions, respectively includes pixel electrodes, and arranged along a first pixel column to a sixth pixel column, gate lines including pairs of two adjacent gate lines for each pixel row in the row direction, data lines including a first data line at a left side of the first pixel column, a second data line between the second and third pixel columns, a third data line between the fourth and fifth pixel columns, and a fourth data line at a right side of the sixth pixel column; and common voltage lines including a first common voltage line between the first and second pixel columns, a second common voltage line between the third and fourth pixel columns, and a third common voltage line between the fifth and sixth pixel columns.