Abstract: An integrated circuit is provided which includes a multi-state circuit with a first PMOS transistor and a first NMOS transistor. In an active mode, the multi-state circuit is operable to switch between a first state in which the first PMOS transistor is turned on and the first NMOS transistor is turned off and a second state in which the first PMOS transistor is turned off and the first NMOS transistor is turned on. A power source NMOS transistor has a drain connected to a supply voltage terminal and has a source connected to a source of the first PMOS transistor. A power source PMOS transistor has a drain connected to a an effective ground terminal and has a source connected to a source of the first NMOS transistor.

Abstract: An integrated circuit is provided which includes a multi-state circuit with a first PMOS transistor and a first NMOS transistor. In an active mode, the multi-state circuit is operable to switch between a first state in which the first PMOS transistor is turned on and the first NMOS transistor is turned off and a second state in which the first PMOS transistor is turned off and the first NMOS transistor is turned on. A power source NMOS transistor has a drain connected to a supply voltage terminal and has a source connected to a source of the first PMOS transistor. A power source PMOS transistor has a drain connected to a an effective ground terminal and has a source connected to a source of the first NMOS transistor.

Abstract: An integrated circuit is provided comprising a latch circuit including, a first inverter including a first high threshold voltage PMOS transistor and a first high threshold voltage NMOS transistor with a first data node comprising interconnected source/drains (S/D) of the first PMOS and NMOS transistors; a second inverter including a second high threshold voltage PMOS transistor and a second high threshold voltage NMOS transistor with a second data node comprising interconnected source/drains (S/D) of the second PMOS and NMOS transistors; wherein the gates of the first PMOS and first NMOS transistors are coupled to the second data node; wherein the gates of the second PMOS and second NMOS transistors are coupled to the first data node; a first low threshold voltage access transistor including a first S/D coupled to the first data node and to the gate of the second PMOS transistor and to the gate of the second NMOS transistor and including a second S/D coupled to a first data access node and including a gate c

Abstract: The present invention relates to the improvement of a phase noise characteristics of supply voltage in VCO. The delay in delay cells may be controlled to use the resistor of a transmission gate instead of a tail current. That is, the delay of cells is controlled by applying the overdrive voltage in transmission gate. And the self-regulating may be possible to composing a feedback inside the delay cells.

Abstract: A new CMOS dynamic logic family is based on parallel dynamic logic concept, avoiding stacked evaluation transistors. The basic configuration for the logic family is a pair of clock transistors including a NMOS and a PMOS transistor having parallel logic transistors connected between the NMOS and PMOS clock transistors. The parallel-connected transistors have gates for logic inputs and an output originating from one of a commonly connected source or drain. The family may provide NOR, NAND, OR, and AND. The family also includes BUF and INV. The BUF logic gate is realized with opposing NMOS and PMOS and an INV, while the INV uses either a single NMOS or PMOS transistor in place of the parallel-connected transistors. A speed enhanced skewed static logic gate is also provided. The speed enhanced gate uses a plurality of PMOS transistors and a plurality of NMOS transistors matched and joined as a plurality of separate gate inputs.

Abstract: A switching mechanism of a circuit breaker for a gas insulated switchgear is able to extinguish arc gas by changing a volume of a compressing chamber without increasing a stroke of a movable cylinder and without increasing required output power of an actuator.

Abstract: A CMOS sequential logic circuit for an edge triggered flip-flop to lower power consumption in very large scale integrated (VLSI) circuit designs is disclosed. The circuit includes a plurality of PMOS transistors and a plurality of NMOS transistors. The PMOS and NMOS transistors are matched and joined as a data-sampling front end and a data-transferring back end to provide an output based on an input signal fed to a pair of transistor gates. Outputs from the pair of transistor gates charge and discharge internal nodes which connect the data-sampling front end to the data-transferring back end. The internal nodes also include a first latch that connects to a first internal node, and a second latch that connects to a second internal node. The latches prevent a floating voltage state for each of the first and second internal nodes and reduce power consumption during flip-flop transitions.

Abstract: A delay locked loop (DLL) clock generator circuit is provided for generating a clock signal Clk according to a pair of input signals to the circuit. One of the input signals is a reference signal, and the second input signal is a feedback signal of a voltage controlled delay line circuit. The DLL circuit includes a phase detector that can be reset to expand the locking range for detecting a phase difference between the reference signal and the feedback signal. Based on the detected phase difference, the phase detector provides an output signal that is further processed by the DLL circuit to generate a number of delayed signals to a frequency multiplier. Using the delayed signals, the frequency multiplier generates a frequency multiplied clock signal having a frequency that is a multiple of the frequency of the reference signal.

Abstract: A reverse biasing logic circuit is disclosed for limiting standby leakage electric current losses during circuit operation. The circuit includes a logic function circuit having one or more logic transistors that receive an input and perform a logic function operation to generate an output. A power source transistor connects to the logic function circuit and receives a control signal that changes node voltages of the one or more logic transistors between an active mode and a standby mode. During the standby mode, the power source transistor causes reverse biasing of at least one of the one or more logic transistors which prevents a leakage electric current flow between the power source transistor and the one or more logic transistors.

Abstract: An integrated circuit is provided which includes a multi-state circuit with a first PMOS transistor and a first NMOS transistor. In an active mode, the multi-state circuit is operable to switch between a first state in which the first PMOS transistor is turned on and the first NMOS transistor is turned off and a second state in which the first PMOS transistor is turned off and the first NMOS transistor is turned on. A power source NMOS transistor has a drain connected to a supply voltage terminal and has a source connected to a source of the first PMOS transistor. A power source PMOS transistor has a drain connected to a an effective ground terminal and has a source connected to a source of the first NMOS transistor.

Abstract: An integrated circuit is provided comprising a latch circuit including, a first inverter including a first high threshold voltage PMOS transistor and a first high threshold voltage NMOS transistor with a first data node comprising interconnected source/drains (S/D) of the first PMOS and NMOS transistors; a second inverter including a second high threshold voltage PMOS transistor and a second high threshold voltage NMOS transistor with a second data node comprising interconnected source/drains (S/D) of the second PMOS and NMOS transistors; wherein the gates of the first PMOS and first NMOS transistors are coupled to the second data node; wherein the gates of the second PMOS and second NMOS transistors are coupled to the first data node; a first low threshold voltage access transistor including a first S/D coupled to the first data node and to the gate of the second PMOS transistor and to the gate of the second NMOS transistor and including a second S/D coupled to a first data access node and including a gate c

Abstract: Methods and circuits are described for reducing power consumption within digital logic circuits by blocking the passage of clock signal transitions to the logic circuits when the clock signal would not produce a desired change of state within the logic circuit, such as at inputs, intermediary nodes, outputs, or combinations. By way of example, the incoming clock is blocked if a given set of logic inputs will not result in an output change of state if a clock signal transition were to be received. By way of further example, the incoming clock is blocked in a data flip-flop if the input signal matches the output signal, such that receipt of a clock transition would not produce a desired change of state in the latched output. The invention may be utilized for creating lower power combinatorial and/or sequential logic circuit stages subject to less unproductive charging and discharging of gate capacitances.

Abstract: An integrated circuit is provided comprising a first NMOS transistor; a first PMOS transistor; a second NMOS transistor; a second PMOS transistor; a first bias voltage node coupled to a first source/drain of the first NMOS transistor; a second bias voltage node coupled to a first source/drain of the second PMOS; a third bias voltage node coupled to a gate of the first PMOS transistor; a fourth bias voltage node coupled to a gate of the second NMOS transistor; a pull-up node coupling a second source/drain of the first NMOS transistor to a first source/drain of the first PMOS transistor; a pull-down node coupling a second source/drain of the second PMOS transistor to a first source/drain of the second NMOS transistor; an input node; a storage node coupling a second source/drain of the first PMOS transistor to a second source/drain of the second NMOS transistor; an output node; an input switch coupled to controllably communicate an input data value from the input node to a gate of the first NMOS transistor and t

Abstract: A double cup capable of containing snacks and drinks in a separate manner is provided so as to allow consumers to enjoy snacks and drinks at the same time. The double cup is divided into an upper section and a lower section through an auxiliary member having a drinking straw insertion portion, and the auxiliary member is a disk having a tapered outer periphery or an auxiliary cup having a shape same as that of the main cup. The auxiliary member is an auxiliary cup having a recess of a predetermined shape formed at the side surface of the auxiliary member, and the auxiliary cup has a stopper formed along an outer periphery of the top of the auxiliary cup in such a manner that an outer periphery of the auxiliary cup excluding the recess contacts an inner periphery of the main cup when inserted into the main cup, and the stopper is disposed onto the top of the main cup. The space defined between the main cup and the recess of the auxiliary cup forms a drinking straw insertion portion.

Abstract: A delay locked loop (DLL) clock generator circuit is provided for generating a clock signal Clk according to a pair of input signals to the circuit. One of the input signals is a reference signal, and the second input signal is a feedback signal of a voltage controlled delay line circuit. The DLL circuit includes a phase detector that can be reset to expand the locking range for detecting a phase difference between the reference signal and the feedback signal. Based on the detected phase difference, the phase detector provides an output signal that is further processed by the DLL circuit to generate a number of delayed signals to a frequency multiplier. Using the delayed signals, the frequency multiplier generates a frequency multiplied clock signal having a frequency that is a multiple of the frequency of the reference signal.

Abstract: The present invention relates to the improvement of a phase noise characteristics of supply voltage in VCO. The delay in delay cells may be controlled to use the resistor of a transmission gate instead of a tail current. That is, the delay of cells is controlled by applying the overdrive voltage in transmission gate. And the self-regulating may be possible to composing a feedback inside the delay cells.

Abstract: A semiconductor integrated circuit wafer tester includes a supporting plate on which a semiconductor wafer may be positioned and a tester head having a circular top plate installed a predetermined distance away from the supporting plate, wherein a probe card in the tester head that includes a circular printed circuit board having a diameter of at least 400 mm (15.75 inches) that is connected to the top plate and having a plurality of probe units formed on the printed circuit board allows electrical parameters of multiple chips formed on the semiconductor wafer to be measured simultaneously.

Abstract: A switching mechanism of a circuit breaker for a gas insulated switchgear is able to extinguish arc gas by changing a volume of a compressing chamber without increasing a stroke of a movable cylinder and without increasing required output power of an actuator.

Abstract: A new CMOS skewed static logic gate is provided having a logic function circuit and a positive feedback or accelerator circuit. The skewed gate uses a plurality of transistors matched and joined as a plurality of separate gate inputs to form the logic function circuit and the accelerator circuit. The accelerator circuit, which connects to an output of the logic function circuit, provides acceleration to the evaluation performed by the logic function circuit. The logic function circuit includes an evaluation path connected to a set of output transistors that connect to transistors of the accelerator circuit. The evaluation path includes a stacked set of low threshold voltage (Vt) transistors, which have a lower Vt than the set of output transistors. The output transistors are configured to receive a first input signal to precharge an output of the CMOS skewed static logic gate prior to the skewed gate receiving a second input signal.

Abstract: A double cup capable of containing snacks and drinks in a separate manner is provided so as to allow consumers to enjoy snacks and drinks at the same time. The double cup is divided into an upper section and a lower section through an auxiliary member having a drinking straw insertion portion, and the auxiliary member is a disk having a tapered outer periphery or an auxiliary cup having a shape same as that of the main cup. The auxiliary member is an auxiliary cup having a recess of a predetermined shape formed at the side surface of the auxiliary member, and the auxiliary cup has a stopper formed along an outer periphery of the top of the auxiliary cup in such a manner that an outer periphery of the auxiliary cup excluding the recess contacts an inner periphery of the main cup when inserted into the main cup, and the stopper is disposed onto the top of the main cup. The space defined between the main cup and the recess of the auxiliary cup forms a drinking straw insertion portion.