Abstract: A CMOS sequential logic circuit for an edge triggered flip-flop to lower power consumption in very large scale integrated (VLSI) circuit designs is disclosed. The circuit includes a plurality of PMOS transistors and a plurality of NMOS transistors. The PMOS and NMOS transistors are matched and joined as a data-sampling front end and a data-transferring back end to provide an output based on an input signal fed to a pair of transistor gates. Outputs from the pair of transistor gates charge and discharge internal nodes which connect the data-sampling front end to the data-transferring back end. The internal nodes also include a first latch that connects to a first internal node, and a second latch that connects to a second internal node. The latches prevent a floating voltage state for each of the first and second internal nodes and reduce power consumption during flip-flop transitions.

Abstract: An integrated circuit is provided which includes a multi-state circuit with a first PMOS transistor and a first NMOS transistor. In an active mode, the multi-state circuit is operable to switch between a first state in which the first PMOS transistor is turned on and the first NMOS transistor is turned off and a second state in which the first PMOS transistor is turned off and the first NMOS transistor is turned on. A power source NMOS transistor has a drain connected to a supply voltage terminal and has a source connected to a source of the first PMOS transistor. A power source PMOS transistor has a drain connected to a an effective ground terminal and has a source connected to a source of the first NMOS transistor.

Abstract: A semiconductor integrated circuit wafer tester includes a supporting plate on which a semiconductor wafer may be positioned and a tester head having a circular top plate installed a predetermined distance away from the supporting plate, wherein a probe card in the tester head that includes a circular printed circuit board having a diameter of at least 400 mm (15.75 inches) that is connected to the top plate and having a plurality of probe units formed on the printed circuit board allows electrical parameters of multiple chips formed on the semiconductor wafer to be measured simultaneously.

Abstract: A new CMOS dynamic logic family is based on parallel dynamic logic concept, avoiding stacked evaluation transistors. The basic configuration for the logic family is a pair of clock transistors including a NMOS and a PMOS transistor having parallel logic transistors connected between the NMOS and PMOS clock transistors. The parallel-connected transistors have gates for logic inputs and an output originating from one of a commonly connected source or drain. The family may provide NOR, NAND, OR, and AND. The family also includes BUF and INV. The BUF logic gate is realized with opposing NMOS and PMOS and an INV, while the INV uses either a single NMOS or PMOS transistor in place of the parallel-connected transistors. A speed enhanced skewed static logic gate is also provided. The speed enhanced gate uses a plurality of PMOS transistors and a plurality of NMOS transistors matched and joined as a plurality of separate gate inputs.

Abstract: A new CMOS skewed static logic gate is provided having a logic function circuit and a positive feedback or accelerator circuit. The skewed gate uses a plurality of transistors matched and joined as a plurality of separate gate inputs to form the logic function circuit and the accelerator circuit. The accelerator circuit, which connects to an output of the logic function circuit, provides acceleration to the evaluation performed by the logic function circuit. The logic function circuit includes an evaluation path connected to a set of output transistors that connect to transistors of the accelerator circuit. The evaluation path includes a stacked set of low threshold voltage (Vt) transistors, which have a lower Vt than the set of output transistors. The output transistors are configured to receive a first input signal to precharge an output of the CMOS skewed static logic gate prior to the skewed gate receiving a second input signal.

Abstract: A reverse biasing logic circuit is disclosed for limiting standby leakage electric current losses during circuit operation. The circuit includes a logic function circuit having one or more logic transistors that receive an input and perform a logic function operation to generate an output. A power source transistor connects to the logic function circuit and receives a control signal that changes node voltages of the one or more logic transistors between an active mode and a standby mode. During the standby mode, the power source transistor causes reverse biasing of at least one of the one or more logic transistors which prevents a leakage electric current flow between the power source transistor and the one or more logic transistors.

Abstract: An asynchronous mode transfer (ATM) switch conducting switching based upon the calculation of weights for entries corresponding to cells in an input queue to achieve a high throughput rate which avoids head of line blocking. The switch includes a cell scheduler driven by the iterative resolution of a traffic matrix formed by highest priority entries for each of a plurality of output ports queued in each of a plurality input queues each having separate virtual queues corresponding to the output ports. Conflicts in the matrix are resolved according to weight so that one entry per one row is chosen to be transmitted in parallel. Selection of winning entries from among a group of conflicting entries during any step are resolved by selecting the heaviest weighted entry and leaving the remaining ports maximum satisfactory transmission opportunities.

Abstract: An ESD/EOS protection circuit (100) for protecting an integrated circuit. A MOS transistor (102) is arranged in a multi-finger configuration having a plurality of drain regions (124), a plurality of source regions (122) and a plurality of gates (118). A first metal layer (162) substantially covers each of the drain regions (124) and is in contact with each of the drain regions (124) via drain contacts (130). A second metal layer (154) substantially covers each of the source regions (122) and is in contact with each of the source regions via source contacts (128). A plurality of source contacts (128) are located at a minimum distance from gates (118). Metal-to-metal contacts (160) connect a third metal layer (156) with the second metal layer (154) over each of the source regions (122).

Abstract: An ESD/EOS protection circuit 10. Trigger nMOS transistor M1 has a drain 20 connected to a voltage pad 22, a gate 24 connected to ground 26 and a source 28 connected to ground 26 through source resistor R.sub.e. Switch control nMOS transistor M2 has a drain 30, a gate 34 connected to source 28 of transistor M1, and a source 38 connected to ground 26. Current controlled switch (CCS) 40 is connected to voltage pad 22, ground 26 and drain 30 of transistor M2. CCS 40 is a bipolar pnp-based current controlled switch.

Abstract: An ESD/EOS protection circuit (100) for protecting an integrated circuit. A MOS transistor (102) is arranged in a multi-finger configuration having a plurality of drain regions (124), a plurality of source regions (122) and a plurality of gates (118). A first metal layer (162) substantially covers each of the drain regions (124) and is in contact with each of the drain regions (124) via drain contacts (130). A second metal layer (154) substantially covers each of the source regions (122) and is in contact with each of the source regions via source contacts (128). A plurality of source contacts (128) are located at a minimum distance from gates (118). Metal-to-metal contacts (160) connect a third metal layer (156) with the second metal layer (154) over each of the source regions (122).