Abstract: A semiconductor apparatus includes first and second vias, a first circuit unit, a second circuit unit and a third circuit unit. The first and second vias electrically connect a first chip and a second chip with each other. The first circuit unit is disposed in the first chip, receives test data, and is connected with the first via. The second circuit unit is disposed in the first chip, and is connected with the second via and the first circuit unit. The third circuit unit is disposed in the second chip, and is connected with the first via. The first circuit unit outputs an output signal thereof to one of the first via and the second circuit unit in response to a first control signal.

Abstract: There are provided a thin film transistor substrate for transflective liquid crystal display device (LCD) and a manufacturing method thereof, which can reduce manufacturing cost and simplifying manufacturing processes. In the method, a thin film transistor is formed on a reflection region of a device substrate defined by the reflection region and a transmission region. A passivation layer is formed on the thin film transistor so as to expose a drain electrode of the thin film transistor and to cover the thin film transistor. A pixel electrode is formed on the transmission and reflection regions. The pixel electrode has a structure of a first pixel electrode electrically connected to the drain electrode and a second pixel electrode formed to have an embossed pattern on the first pixel electrode. A reflective layer is formed on the second electrode pixel having the embossed pattern on the reflection region.

Abstract: A semiconductor system, a semiconductor memory apparatus, and a method for input/output of data using the same are disclosed. The semiconductor system includes a controller and a memory apparatus where the controller is configured to transmit a clock signal, a data output command, an address signal, and a second strobe signal to a memory apparatus. The memory apparatus is configured to provide data to the controller in synchronization with the second strobe signal, and in response to the clock signal, the data output command, the address signal, and the second strobe signal received from the controller.

Abstract: Disclosed herein is an inertial sensor. The inertial sensor 100 according to preferred embodiments of the present invention includes: a membrane 110; a mass body 120 disposed under the membrane 110; a piezoelectric body 130 formed on the membrane 110 to drive the mass body 120; and trenches 140 formed by being collapsed in a thickness direction of the piezoelectric body 130 so as to vertically meet a direction in which the mass body 120 is driven. By this configuration, the trenches are formed by being collapsed in a thickness direction of the piezoelectric body 130 to provide directivity while retaining the rigidity of the piezoelectric body 130 to prevent a wave from being propagated in an unnecessary direction, thereby driving the inertial sensor 100 in a desired specific direction.

Abstract: There is provided a silicon substrate including: a first connection part connected to a manifold and having a first width of a first size; a second connection part connected to a pressure chamber and having a second width of a second size; and a restrictor part connecting the first connection part to the second connection part and having a third width of a third size smaller than the first size or the second size, wherein a boundary part connecting the restrictor part to the first connection part or the restrictor part to the second connection part is formed to be curved.

Abstract: A semiconductor apparatus includes first and second vias, a first circuit unit, a second circuit unit and a third circuit unit. The first and second vias electrically connect a first chip and a second chip with each other. The first circuit unit is disposed in the first chip, receives test data, and is connected with the first via. The second circuit unit is disposed in the first chip, and is connected with the second via and the first circuit unit. The third circuit unit is disposed in the second chip, and is connected with the first via. The first circuit unit outputs an output signal thereof to one of the first via and the second circuit unit in response to a first control signal.

Abstract: A semiconductor memory apparatus includes: a memory cell area including a plurality of memory cell arrays stacked therein, each memory cell array having a plurality of memory cells integrated and formed therein to store data and a plurality of through-lines formed therein to transmit signals; and a control logic area configured to generate parity bits using a data signal inputted to the memory cell area and transmit the generated parity bits and the data signal to different through-lines.

Abstract: A base member including two-step recesses and a hard disk drive (HDD) including the same. The HDD includes a base member; a spindle motor installed in the base member; a data storage disk assembled to the spindle motor; and an actuator rotatably installed in the base member and for moving a read/write head to a desired position on the disk, wherein the base member includes: a first floor surface disposed in a region facing the disk and having a center portion in which the spindle motor is installed; a shroud formed on a circumference of the first floor surface and extending the exterior circumference of the disk; and two-step recesses formed in an operating region of the actuator, wherein the two-step recesses comprise a first step recess formed on the first floor surface and a second step recess formed on a floor surface of the first step recess.

Abstract: A semiconductor apparatus includes a plurality of semiconductor chips which are stacked; and an auxiliary semiconductor chip configured to recover and transmit signals of the plurality of semiconductor chips through a plurality of through vias which extend vertically, at a predetermined time interval.

Abstract: A system in package (SIP) semiconductor system includes a memory device, a controller, a first input/output terminal, a test control unit, and a second input/output terminal. The controller communicates with the memory device. The first input/output terminal performs communication between the controller and a device external to the SIP semiconductor system. The test control unit controls a predetermined test mode of the memory device. The second input/output terminal performs communication between the test control unit and at least the device external to the SIP semiconductor system.

Abstract: A semiconductor system, a semiconductor memory apparatus, and a method for input/output of data using the same are disclosed. The semiconductor system includes a controller and a memory apparatus where the controller is configured to transmit a clock signal, a data output command, an address signal, and a second strobe signal to a memory apparatus. The memory apparatus is configured to provide data to the controller in synchronization with the second strobe signal, and in response to the clock signal, the data output command, the address signal, and the second strobe signal received from the controller.

Abstract: An Inkjet head according to an exemplary embodiment of the present invention includes an ink storage unit including an inner storage space, a head unit connected to the ink storage unit, and a plurality of nozzles discharging the ink, wherein the floors of the inner storage space of the ink storage unit form a step. Accordingly, in the Inkjet head of an exemplary embodiment of the present invention, the floors of the inner storage space of the ink storage unit form a step, and the ceiling of the inner flow space of the head unit is inclined, thereby preventing the ink vapor from being confined inside the head unit. Therefore, the ink to be discharged through the nozzle flows in a predetermined direction and does not include ink vapor, thereby preventing discharge deterioration.