Abstract: An environmentally friendly method of coating copper nanowires to reduce oxidation and/or increase electrical/thermal conductivity of the copper nanowires. In one embodiment, a method for coating copper nanowires includes preparing a first solution including a dipolar aprotic organic compound, adding copper nanowires to the first solution under stirring while maintaining the first solution at a pre-determined temperature, preparing a second solution including an oxidation resistant metal, coating the copper nanowires in the oxidation resistant metal by adding the second solution to the first solution under stirring and while maintaining the first solution at the pre-determined temperature.

Abstract: A method of manufacturing a capacitor-embedded printed circuit board using a first conductive layer formed on one side of an insulation layer, the method including: forming a second conductive layer on one side of the first conductive layer; forming a second electrode by removing a portion of the second conductive layer; forming a first electrode by removing a portion of the first conductive layer in correspondence with the second electrode; and forming a dielectric layer on one side of the second electrode.

Abstract: The present invention relates to a chip embedded printed circuit board and a manufacturing method thereof and provides a chip embedded printed circuit board including: an insulating layer having vias formed therethrough; a first chip and a second chip embedded in the insulating layer and having pads, which are respectively exposed to upper and lower surfaces of the insulating layer, on one surfaces thereof; an upper pattern formed on the upper surface of the insulating layer to be connected to the pads of the first chip and the vias; and a lower pattern formed on the lower surface of the insulating layer to be connected to the pads of the second chip and the vias. Also, the present invention provides a manufacturing method of a chip embedded printed circuit board.

Abstract: An electronic component package includes: a first insulation layer; an electronic component mounted in one surface of the first insulation layer; a heat sink formed with a cavity corresponding to the electronic component, bonded to the one surface of the first insulation layer to cover the electronic component, and formed with an inset hole and with an inlet hole; an adhesive charged in the cavity; and a circuit pattern formed in another surface of the first insulation layer.

Abstract: An electronic component package and a manufacturing method thereof are disclosed. The electronic component package manufacturing method, which includes mounting an electronic component in one surface of a first insulation layer; bonding a heat sink to the one surface of the first insulation layer, corresponding to the electronic component, to cover the electronic component, the heat sink being formed with a cavity; charging the cavity with an adhesive; and forming a circuit pattern in the other surface of the first insulation layer, can prevent a void from being generated in the adhesive, make the handling stable and make the size small by allowing the heat sink formed with the cavity to cover the electronic component before the pattern build-up and supplying the adhesive through one side of the cavity while providing negative pressure through the other side.

Abstract: Disclosed herein is an electronic component-embedded printed circuit board including: a base plate including an insulating resin layer and circuit layers; and an electronic component embedded in the insulating resin layer, wherein the insulating resin layer has a thickness 1.3˜3 times greater than that of the electronic component. The electronic component-embedded printed circuit board has an optimum thickness ratio of its constituents in order to minimize the warpage thereof at the time of manufacturing the same.

Abstract: The present invention relates to a chip embedded printed circuit board and a manufacturing method thereof. The present invention provides the chip embedded printed circuit board including an insulating layer embedding a chip provided with posts at an upper part, vias formed through the insulating layer, upper patterns formed at the upper part of the insulating layer to be connected to the posts and the vias and lower patterns formed at a lower part of the insulating layer to be connected to the vias, and the manufacturing method thereof.

Abstract: Disclosed herein are a wafer level package for heat dissipation and a method of manufacturing the same. The wafer level package includes a heat dissipation plate including a cavity and a hole, a die including a pad disposed in the cavity of the heat dissipation plate in a face-up manner, a thermal conductive adhesive disposed between the die and an inner wall of the cavity and disposed in the hole, and a redistribution layer connected at one end to the pad and at the other end extended. The wafer level package protects the die from external environments and enables the die to be easily flush with the heat dissipation plate.

Abstract: A method of manufacturing a capacitor-embedded printed circuit board that includes fabricating a capacitor substrate having at least one inner electrode formed on one side of a dielectric layer; aligning a semi-cured insulation layer with one side of a core layer, and aligning the capacitor substrate with the semi-cured insulation layer such that the inner electrode faces the semi-cured insulation layer; and collectively stacking the core layer, the semi-cured insulation layer, and the capacitor substrate.

Abstract: Disclosed herein are a wafer level package for heat dissipation and a method of manufacturing the same. The wafer level package includes a heat dissipation plate including a cavity and a hole, a die including a pad disposed in the cavity of the heat dissipation plate in a face-up manner, a thermal conductive adhesive disposed between the die and an inner wall of the cavity and disposed in the hole, and a redistribution layer connected at one end to the pad and at the other end extended. The wafer level package protects the die from external environments and enables the die to be easily flush with the heat dissipation plate.

Abstract: A method for manufacturing a wafer level package including: forming a redistribution line connected to a top surface of a die pad on a wafer with the die pad; additionally preparing a carrier film including a metal post with a concave central portion on one surface; bonding the metal post to a top surface of the redistribution line; molding a space between the metal posts with a molding resin; and removing the carrier film.

Abstract: A method of manufacturing a capacitor-embedded printed circuit board, the method including providing a substrate on which a first metal layer, a dielectric layer and an adhesive resin layer are stacked on the order thereof; etching a part of the first metal layer to form a first electrode and a first circuit pattern; compressing a surface of the substrate, on which the first electrode is formed, onto a core board by interposing an insulation resin layer; forming a second electrode and a second circuit pattern on the adhesive resin layer; stacking an insulation board on the substrate such that the second electrode and the second circuit pattern are covered; and forming a third circuit pattern on the insulation board.

Abstract: A method of manufacturing a wafer level package including: separating chips by dicing a wafer; forming a removable resin layer in a space between the separated chips and at upper parts thereof; separating the chips by dicing the removable resin layer; mounting the chips separated in a state of being surrounded by the removable resin layer, on a carrier plate; forming a molding material on the carrier plate to cover the removable resin layer; separating the carrier plate from the chips; forming a dielectric layer having redistribution lines connected to the chips, on the chips exposed by separating the carrier plate; and forming a solder resist layer on the dielectric layer to expose portions of the redistribution lines.

Abstract: A wafer level package includes a chip, a removable resin layer, a molding material, a dielectric layer, redistribution lines and a solder resist. The removable resin layer is formed to surround side surfaces and a lower surface of the chip. The molding material is formed on the lower surface of the removable resin layer. The dielectric layer is formed over the removable resin layer including the chip and having via holes to expose portions of the chip. The redistribution lines are formed on the dielectric layer including insides of the via holes to be connected to the chip. The solder resist layer is formed on the dielectric layer to expose portions of the redistribution lines.

Abstract: A method for manufacturing a wafer level package including: forming a redistribution line connected to a top surface of a die pad on a wafer with the die pad; additionally preparing a carrier film including a metal post with a concave central portion on one surface; bonding the metal post to a top surface of the redistribution line; molding a space between the metal posts with a molding resin; and removing the carrier film.

Abstract: A semiconductor chip package and a printed circuit board having an embedded semiconductor chip package are disclosed. The semiconductor chip package may include a semiconductor chip that has at least one chip pad formed on one side, and a capacitor formed on the other side of the semiconductor chip.

Abstract: Disclosed herein are a die package and a method of manufacturing the die package. A solder layer is formed on a lower surface of a die. The die is self-aligned and attached to a support plate using surface tension between the solder layer and a metal layer of the support plate, thus reducing attachment lead time of the die.

Abstract: A printed circuit board and a manufacturing method thereof are disclosed. The method in accordance with an embodiment of the present invention includes: providing a substrate on which a first insulation layer, a first circuit pattern, a second insulation layer and a resin layer are successively laminated; boring a through-hole penetrating the substrate; forming roughness on the resin layer by a desmear process; forming a via making an electrical connection between layers through the through-hole; and forming a second circuit pattern on the resin layer having roughness formed thereon.

Abstract: Disclosed herein is a wafer level packaging image sensor module, including a wafer including an image sensor, a circuit portion and a lower electrode on one side thereof, a lens actuator disposed on the lower electrode and made of electroactive polymer, an upper electrode disposed on the lens actuator, and a lens unit disposed on the upper electrode to allow light to be transmitted to the image sensor therethrough. The wafer level packaging image sensor module includes the lens actuator made of electroactive polymer, and thus it enables realization of the autofocusing of the wafer level packaging image sensor module.