Abstract: A includes an element isolation region, a first active region bounded by the element isolation region and that extends in a first direction and includes first and second parts disposed at a first level, and a third part disposed at a second level located above the first level, and a gate electrode disposed inside each of the element isolation region and the first active region and that extends in a second direction different from the first direction. The second part is spaced apart in the first direction from the first part, and the third part contacts each of the first and second parts. A first width in the second direction of the first part is less than a second width in the second direction of the third part.

Abstract: A semiconductor device includes a device isolation layer defining first and second active regions, a buried contact connected to the second active region, and first and second bit line structures disposed on the first and second active regions. Each of the first and second bit line structures comprises a bit line contact part and a bit line pass part. The bit line contact part is electrically connected to the first active region. The bit line pass part is disposed on the device isolation layer. A height of a lowest part of the buried contact is smaller than a height of a lowest part of the bit line pass part. The height of the lowest part of the buried contact is greater than a height of a lowest part of the bit line contact part. A lower end of the bit line pass part is buried in the second active region.

Abstract: A semiconductor device includes a plurality of conductive structures arranged on a substrate and spaced apart from each other in a second direction substantially perpendicular to a first direction, in which each of the plurality of conductive structures extends in the first direction. A plurality of contact structures are arranged between the conductive structures in an alternating arrangement and spaced apart from each other in the first direction. A plurality of insulation structures are arranged in a space between the conductive structures and between the contact structures. A plurality of air spacers are arranged between the alternating arrangement of the plurality of conductive structures and the plurality of contact structures, respectively and spaced apart from each other in the first direction.

Abstract: Disclosed is a vehicle door checker that includes: an open lever configured to rotate a pawl in an open direction; a handle open lever having a link pin insertion groove; an inner handle lever connected to an inner handle cable and including a first contact end and a second contact end configured to come into contact with the handle open lever while being rotated in the open direction; an inner link lever configured to come into contact with the first contact end when the inner handle lever is rotated in the open direction; an inner lock lever configured to share a rotation axis with the inner link lever; an elastic member fastened between the inner link lever and the inner lock lever; and a link including a link pin interlocked with rotation of the inner lock lever in an unlocking direction.

Abstract: A semiconductor device includes a device isolation layer defining first and second active regions, a buried contact connected to the second active region, and first and second bit line structures disposed on the first and second active regions. Each of the first and second bit line structures comprises a bit line contact part and a bit line pass part. The bit line contact part is electrically connected to the first active region. The bit line pass part is disposed on the device isolation layer. A height of a lowest part of the buried contact is smaller than a height of a lowest part of the bit line pass part. The height of the lowest part of the buried contact is greater than a height of a lowest part of the bit line contact part. A lower end of the bit line pass part is buried in the second active region.

Abstract: An integrated circuit device may include a support pattern over a substrate, a lower electrode pattern and a dielectric structure over the substrate, and an upper electrode structure on the dielectric structure. The support pattern may include a first support structure extending in a vertical direction. The lower electrode pattern may be between the support pattern and the dielectric structure. The lower electrode pattern may include a first group of N (e.g., an integer of 4 or more) lower electrodes that are spaced apart from each other and may extend in the vertical direction to a first level above the substrate. The dielectric structure may include a first dielectric protrusion that extends in the vertical direction and surrounds the first support structure and the first group of N lower electrodes. The upper electrode structure may include a first upper electrode protrusion that surrounds the first dielectric protrusion.

Abstract: A semiconductor device includes a device isolation layer defining first and second active regions, a buried contact connected to the second active region, and first and second bit line structures disposed on the first and second active regions. Each of the first and second bit line structures comprises a bit line contact part and a bit line pass part. The bit line contact part is electrically connected to the first active region. The bit line pass part is disposed on the device isolation layer. A height of a lowest part of the buried contact is smaller than a height of a lowest part of the bit line pass part. The height of the lowest part of the buried contact is greater than a height of a lowest part of the bit line contact part. A lower end of the bit line pass part is buried in the second active region.

Abstract: A includes an element isolation region, a first active region bounded by the element isolation region and that extends in a first direction and includes first and second parts disposed at a first level, and a third part disposed at a second level located above the first level, and a gate electrode disposed inside each of the element isolation region and the first active region and that extends in a second direction different from the first direction. The second part is spaced apart in the first direction from the first part, and the third part contacts each of the first and second parts. A first width in the second direction of the first part is less than a second width in the second direction of the third part.

Abstract: First and second mask layers are formed on a target layer. The second mask layer is patterned to form second mask patterns each of which having a rhomboid shape with a first diagonal length and a second diagonal length. A trimming process is performed on the second mask patterns to form second masks by etch. First portions of first opposite vertices of each second mask pattern are etched more than second portions of second opposite vertices of each second mask pattern. A first diagonal length between the first opposite vertices is greater than a second diagonal length between the second opposite vertices. The first mask layer is patterned to form first masks by etching the first mask layer using the second masks as an etching mask. The target layer is patterned to form target patterns by etching the target layer using the first masks as an etching mask.

Abstract: A semiconductor device includes a device isolation layer defining first and second active regions, a buried contact connected to the second active region, and first and second bit line structures disposed on the first and second active regions. Each of the first and second bit line structures comprises a bit line contact part and a bit line pass part. The bit line contact part is electrically connected to the first active region. The bit line pass part is disposed on the device isolation layer. A height of a lowest part of the buried contact is smaller than a height of a lowest part of the bit line pass part. The height of the lowest part of the buried contact is greater than a height of a lowest part of the bit line contact part. A lower end of the bit line pass part is buried in the second active region.

Abstract: A semiconductor device includes a plurality of conductive structures arranged on a substrate and spaced apart from each other in a second direction substantially perpendicular to a first direction, in which each of the plurality of conductive structures extends in the first direction. A plurality of contact structures are arranged between the conductive structures in an alternating arrangement and spaced apart from each other in the first direction. A plurality of insulation structures are arranged in a space between the conductive structures and between the contact structures. A plurality of air spacers are arranged between the alternating arrangement of the plurality of conductive structures and the plurality of contact structures, respectively and spaced apart from each other in the first direction.

Abstract: A semiconductor device includes: a substrate having active regions defined by a device isolation region; a conductive line extending in a direction on the active regions; insulating liners on both sidewalls of a lower portion of the conductive line that contacts with the active regions; spacers that are apart from the insulating liners in a direction perpendicular to a surface of the substrate and sequentially formed on both sidewalls of an upper portion of the conductive line; a blocking layer arranged at a spacing between a spacer located in the middle of the spacers and the insulating liners and in a recess portion recessed from one end of the spacer located in the middle of the spacers toward the conductive line; and conductive patterns arranged on the active regions on both sides of the spacers.

Abstract: A semiconductor device includes a plurality of conductive structures arranged on a substrate and spaced apart from each other in a second direction substantially perpendicular to a first direction, in which each of the plurality of conductive structures extends in the first direction. A plurality of contact structures are arranged between the conductive structures in an alternating arrangement and spaced apart from each other in the first direction. A plurality of insulation structures are arranged in a space between the conductive structures and between the contact structures. A plurality of air spacers are arranged between the alternating arrangement of the plurality of conductive structures and the plurality of contact structures, respectively and spaced apart from each other in the first direction.

Abstract: An integrated circuit device may include a support pattern over a substrate, a lower electrode pattern and a dielectric structure over the substrate, and an upper electrode structure on the dielectric structure. The support pattern may include a first support structure extending in a vertical direction. The lower electrode pattern may be between the support pattern and the dielectric structure. The lower electrode pattern may include a first group of N (e.g., an integer of 4 or more) lower electrodes that are spaced apart from each other and may extend in the vertical direction to a first level above the substrate. The dielectric structure may include a first dielectric protrusion that extends in the vertical direction and surrounds the first support structure and the first group of N lower electrodes. The upper electrode structure may include a first upper electrode protrusion that surrounds the first dielectric protrusion.

Abstract: First and second mask layers are formed on a target layer. The second mask layer is patterned to form second mask patterns each of which having a rhomboid shape with a first diagonal length and a second diagonal length. A trimming process is performed on the second mask patterns to form second masks by etch. First portions of first opposite vertices of each second mask pattern are etched more than second portions of second opposite vertices of each second mask pattern. A first diagonal length between the first opposite vertices is greater than a second diagonal length between the second opposite vertices. The first mask layer is patterned to form first masks by etching the first mask layer using the second masks as an etching mask. The target layer is patterned to form target patterns by etching the target layer using the first masks as an etching mask.

Abstract: A semiconductor device, including an active region defined in a semiconductor substrate; a first contact plug on the semiconductor substrate, the first contact plug being connected to the active region; a bit line on the semiconductor substrate, the bit line being adjacent to the first contact plug; a first air gap spacer between the first contact plug and the bit line; a landing pad on the first contact plug; a blocking insulating layer on the bit line; and an air gap capping layer on the first air gap spacer, the air gap capping layer vertically overlapping the first air gap spacer, the air gap capping layer being between the blocking insulating layer and the landing pad, an upper surface of the blocking insulating layer being at a height equal to or higher than an upper surface of the landing pad.

Abstract: An integrated circuit device may include a support pattern over a substrate, a lower electrode pattern and a dielectric structure over the substrate, and an upper electrode structure on the dielectric structure. The support pattern may include a first support structure extending in a vertical direction. The lower electrode pattern may be between the support pattern and the dielectric structure. The lower electrode pattern may include a first group of N (e.g., an integer of 4 or more) lower electrodes that are spaced apart from each other and may extend in the vertical direction to a first level above the substrate. The dielectric structure may include a first dielectric protrusion that extends in the vertical direction and surrounds the first support structure and the first group of N lower electrodes. The upper electrode structure may include a first upper electrode protrusion that surrounds the first dielectric protrusion.

Abstract: An integrated circuit device may include a pair of line structures. Each line structure may include a pair of conductive lines extending over a substrate in a first horizontal direction and a pair of insulating capping patterns respectively covering the pair of conductive lines. The integrated circuit device may include a conductive plug between the pair of line structures and a metal silicide film contacting a top surface of the conductive plug between the pair of insulating capping patterns. The conductive plug may have a first width between the pair of conductive lines and a second width between the pair of insulating capping patterns, in a second horizontal direction perpendicular to the first horizontal direction, where the second width is greater than the first width.

Abstract: A semiconductor device includes a substrate having a trench, a bit line in the trench, a first spacer extending along the trench and at least a portion of a side surface of the bit line and in contact with the bit line, and a second spacer disposed within the trench on the first spacer. The bit line is narrower than the trench, and the first spacer includes silicon oxide. A method of forming a semiconductor device includes forming a trench in a substrate, forming a bit line within the first trench of width less than that of the first trench, and forming a first spacer that lines a portion of the trench and includes silicon oxide in contact with at least a portion of a side surface of the bit line, and forming a second spacer over the first spacer in the trench.

Abstract: A semiconductor device includes: a substrate having active regions defined by a device isolation region; a conductive line extending in a direction on the active regions; insulating liners on both sidewalls of a lower portion of the conductive line that contacts with the active regions; spacers that are apart from the insulating liners in a direction perpendicular to a surface of the substrate and sequentially formed on both sidewalls of an upper portion of the conductive line; a blocking layer arranged at a spacing between a spacer located in the middle of the spacers and the insulating liners and in a recess portion recessed from one end of the spacer located in the middle of the spacers toward the conductive line; and conductive patterns arranged on the active regions on both sides of the spacers.