Abstract: Disclosed is a method of manufacturing a polyurethane filter foam having excellent air permeability, elasticity, and restoring force. In the method of manufacturing the polyurethane filter foam, the cell size of the filter foam is made regular by controlling the pressure by adjusting the diameter of the foaming head of a foaming machine, rather than adding a cell opener, cell irregularity caused by poor dispersion of the cell opener is alleviated, and air permeability, porosity, and compression set are excellent.

Abstract: An embodiment of the present disclosure discloses tobacco material including: a center portion including a flavor material; and an outer portion including a tobacco mixture, wherein the outer portion surrounds the center portion.

Abstract: A low profile flat bombe for Liquefied Petroleum Gas (LPG) storage and method for manufacturing the same, may include a flat bombe body including an upper plate having a plurality of first piercing holes and a pump installation hole formed therethrough, a lower plate having a plurality of second piercing holes formed therethrough at positions vertically coinciding with the plurality of first piercing holes, and side plates integrally connecting first and second side end portions of the upper and lower plates, end plates mounted at front and rear openings in the flat bombe body, and support pipes, wherein upper end portions of the support pipes are welded to internal circumferential portions of the plurality of first piercing holes and lower end portions thereof are welded to internal circumferential portions of the plurality of second piercing holes to maintain a vertical distance between the upper and lower plates.

Abstract: A synapse string includes first and second cell strings each having a plurality of memory cell elements connected in series and first switch elements connected to first or second ends of the first and second cell strings, respectively. The memory cell elements of the first cell string and the memory cell elements of the second cell string are in a one-to-one correspondence, and a pair of the memory cell elements being in a one-to-one correspondence has terminals to which a read voltage is applied connected to each other to constitute one synapse morphic element, so that the synapse string includes a plurality of synapse morphic elements connected in series. A synapse string array architecture enables forward propagation and backward propagation by implementing high-density synapse strings, so that the synapse string array architecture can be applied to a neural network capable of inferencing and on-chip learning, along with inference and recognition.

Abstract: A display device includes: a display panel including a display area including pixels and a non-display area including a dummy pixel; a scan driver which supplies a scan signal to the display panel; a data driver which supplies a data signal to the display panel; and a timing controller which supplies a first control signal for controlling the scan driver and a second control signal for controlling the data driver. The dummy pixel is connected to a bad pixel among the pixels in the display area through a repair line, and a connection of the dummy pixel to the repair line is cut off in an initialization phase in which a voltage of an initialization power source is supplied.

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings and support openings are formed through the alternating stack, and memory opening fill structures and support pillar structures are formed in the memory openings and in the support openings, respectively. Via cavities extending to each of the sacrificial material layers are formed through the alternating stack without forming any stepped surfaces in the alternating stack. The via cavities may be formed in areas that do not overlap with the support pillar structures, or in areas that include at least one support pillar structure. Sacrificial via fill structures are formed in the via cavies, and the sacrificial material layers are replaced with electrically conductive layers. The sacrificial via fill structures are removed, and a combination of a tubular dielectric spacer and a contact via structure can be formed in the via cavities.

Abstract: Provided is a binary neural network including: a synapse string array in which multiple synapse strings are sequentially connected. The synapse string includes: first and second cell strings, each including memory cell devices connected in series; and switching devices connected to first ends of two-side ends of the first and second cell strings. The memory cell devices of the first and second cell strings are in one-to-on correspondence to each other, and a pair of the memory cell devices being in one-to-on correspondence to each other have one-side terminals electrically connected to each other to constitute one synapse morphic device. A plurality of the pairs of memory cell devices configured with the first and second cell strings constituting each synapse string constitute a plurality of the synapse morphic devices. The synapse morphic devices of each synapse string are electrically connected to the synapse morphic devices of other synapse strings.

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings and support openings are formed through the alternating stack, and memory opening fill structures and support pillar structures are formed in the memory openings and in the support openings, respectively. Via cavities extending to each of the sacrificial material layers are formed through the alternating stack without forming any stepped surfaces in the alternating stack. The via cavities may be formed in areas that do not overlap with the support pillar structures, or in areas that include at least one support pillar structure. Sacrificial via fill structures are formed in the via cavies, and the sacrificial material layers are replaced with electrically conductive layers. The sacrificial via fill structures are removed, and a combination of a tubular dielectric spacer and a contact via structure can be formed in the via cavities.

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings and support openings are formed through the alternating stack, and memory opening fill structures and support pillar structures are formed in the memory openings and in the support openings, respectively. Via cavities extending to each of the sacrificial material layers are formed through the alternating stack without forming any stepped surfaces in the alternating stack. The via cavities may be formed in areas that do not overlap with the support pillar structures, or in areas that include at least one support pillar structure. Sacrificial via fill structures are formed in the via cavies, and the sacrificial material layers are replaced with electrically conductive layers. The sacrificial via fill structures are removed, and a combination of a tubular dielectric spacer and a contact via structure can be formed in the via cavities.

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings and support openings are formed through the alternating stack, and memory opening fill structures and support pillar structures are formed in the memory openings and in the support openings, respectively. Via cavities extending to each of the sacrificial material layers are formed through the alternating stack without forming any stepped surfaces in the alternating stack. The via cavities may be formed in areas that do not overlap with the support pillar structures, or in areas that include at least one support pillar structure. Sacrificial via fill structures are formed in the via cavies, and the sacrificial material layers are replaced with electrically conductive layers. The sacrificial via fill structures are removed, and a combination of a tubular dielectric spacer and a contact via structure can be formed in the via cavities.

Abstract: A synapse string includes first and second cell strings each having a plurality of memory cell elements connected in series and first switch elements connected to first or second ends of the first and second cell strings, respectively. The memory cell elements of the first cell string and the memory cell elements of the second cell string are in a one-to-one correspondence, and a pair of the memory cell elements being in a one-to-one correspondence has terminals to which a read voltage is applied connected to each other to constitute one synapse morphic element, so that the synapse string includes a plurality of synapse morphic elements connected in series. A synapse string array architecture enables forward propagation and backward propagation by implementing high-density synapse strings, so that the synapse string array architecture can be applied to a neural network capable of inferencing and on-chip learning, along with inference and recognition.

Abstract: Provided is a binary neural network including: a synapse string array in which multiple synapse strings are sequentially connected. The synapse string includes: first and second cell strings, each including memory cell devices connected in series; and switching devices connected to first ends of two-side ends of the first and second cell strings. The memory cell devices of the first and second cell strings are in one-to-on correspondence to each other, and a pair of the memory cell devices being in one-to-on correspondence to each other have one-side terminals electrically connected to each other to constitute one synapse morphic device. A plurality of the pairs of memory cell devices configured with the first and second cell strings constituting each synapse string constitute a plurality of the synapse morphic devices. The synapse morphic devices of each synapse string are electrically connected to the synapse morphic devices of other synapse strings.

Abstract: Provided is synapse strings and synapse string arrays. The synapse string includes: first and second cell strings, each having a plurality of memory cell devices connected in series; and first switch devices, each connected to one of two ends of each of the first and second cell strings. The memory cell devices of the first cell string and the memory cell devices of the second cell string are in one-to-one correspondence to each other, and terminals of pairs of the memory cell devices being in one-to-one correspondence to each other are applied with read voltages and electrically connected to each other to constitute one synapse morphic device, so that the synapse string includes a plurality of synapse morphic devices connected in series. The synapse string includes a peripheral circuit and a reference current source for implementing a function of a neuron.

Abstract: A first material layer, a second material layer, and a photoresist layer may be formed over a substrate. The second material layer may be patterned by transfer of a lithographic pattern therethrough. A conformal spacer layer may be formed over the patterned second material layer in a chamber enclosure of an in-situ deposition-etch apparatus. Spacer films may be formed by anisotropically etching the conformal spacer layer in the chamber enclosure of the in-situ deposition-etch apparatus. The first material layer may be anisotropically etched using a combination of the patterned second material layer and the spacer films as an etch mask in the in-situ deposition-etch apparatus. A high fidelity pattern may be transferred into the first material layer with reduced line edge roughness, reduced line width roughness, and without enlargement of lateral dimensions of openings in the first material layer.

Abstract: Provided is synapse strings and synapse string arrays. The synapse string includes: first and second cell strings, each having a plurality of memory cell devices connected in series; and first switch devices, each connected to one of two ends of each of the first and second cell strings. The memory cell devices of the first cell string and the memory cell devices of the second cell string are in one-to-one correspondence to each other, and terminals of pairs of the memory cell devices being in one-to-one correspondence to each other are applied with read voltages and electrically connected to each other to constitute one synapse morphic device, so that the synapse string includes a plurality of synapse morphic devices connected in series. The synapse string includes a peripheral circuit and a reference current source for implementing a function of a neuron.

Abstract: A first material layer, a second material layer, and a photoresist layer may be formed over a substrate. The second material layer may be patterned by transfer of a lithographic pattern therethrough. A conformal spacer layer may be formed over the patterned second material layer in a chamber enclosure of an in-situ deposition-etch apparatus. Spacer films may be formed by anisotropically etching the conformal spacer layer in the chamber enclosure of the in-situ deposition-etch apparatus. The first material layer may be anisotropically etched using a combination of the patterned second material layer and the spacer films as an etch mask in the in-situ deposition-etch apparatus. A high fidelity pattern may be transferred into the first material layer with reduced line edge roughness, reduced line width roughness, and without enlargement of lateral dimensions of openings in the first material layer.

Abstract: An inductor includes a support having first and second coils formed on first and second surfaces thereof, respectively; a body embedding the support therein so that end portions of the first and second coils are exposed through first and second surfaces of the body opposing each other, and including a first magnetic part disposed in cores of the first and second coils and on upper and lower surfaces of the first and second coils, respectively, and second magnetic parts disposed on upper and lower surfaces of the first magnetic part, respectively; and first and second external electrodes formed on outer surfaces of the body to be electrically connected to the end portions of the first and second coils, respectively. The second magnetic part has a content of a hardening accelerator greater than that of the first magnetic part.

Abstract: Contacts to peripheral devices extending through multiple tier structures of a three-dimensional memory device can be formed with minimal additional processing steps. First peripheral via cavities through a first tier structure can be formed concurrently with formation of first memory openings. Sacrificial via fill structures can be formed in the first peripheral via cavities concurrently with formation of sacrificial memory opening fill structures that are formed in the first memory openings. Second peripheral via cavities through a second tier structure can be formed concurrently with formation of word line contact via cavities that extend to top surfaces of electrically conductive layers in the first and second tier structures. After removal of the sacrificial via fill structures, the first and second peripheral via cavities can be filled with a conductive material to form peripheral contact via structures concurrently with formation of word line contact via structures.