Patents by Inventor Sung Tae Lee

Sung Tae Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11928579
    Abstract: A synapse string includes first and second cell strings each having a plurality of memory cell elements connected in series and first switch elements connected to first or second ends of the first and second cell strings, respectively. The memory cell elements of the first cell string and the memory cell elements of the second cell string are in a one-to-one correspondence, and a pair of the memory cell elements being in a one-to-one correspondence has terminals to which a read voltage is applied connected to each other to constitute one synapse morphic element, so that the synapse string includes a plurality of synapse morphic elements connected in series. A synapse string array architecture enables forward propagation and backward propagation by implementing high-density synapse strings, so that the synapse string array architecture can be applied to a neural network capable of inferencing and on-chip learning, along with inference and recognition.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: March 12, 2024
    Assignee: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Jong-Ho Lee, Sung-Tae Lee
  • Patent number: 11495612
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings and support openings are formed through the alternating stack, and memory opening fill structures and support pillar structures are formed in the memory openings and in the support openings, respectively. Via cavities extending to each of the sacrificial material layers are formed through the alternating stack without forming any stepped surfaces in the alternating stack. The via cavities may be formed in areas that do not overlap with the support pillar structures, or in areas that include at least one support pillar structure. Sacrificial via fill structures are formed in the via cavies, and the sacrificial material layers are replaced with electrically conductive layers. The sacrificial via fill structures are removed, and a combination of a tubular dielectric spacer and a contact via structure can be formed in the via cavities.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: November 8, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yoshinobu Tanaka, Koichi Ito, Hideaki Hasegawa, Akihiro Tobioka, Sung Tae Lee
  • Patent number: 11461624
    Abstract: Provided is a binary neural network including: a synapse string array in which multiple synapse strings are sequentially connected. The synapse string includes: first and second cell strings, each including memory cell devices connected in series; and switching devices connected to first ends of two-side ends of the first and second cell strings. The memory cell devices of the first and second cell strings are in one-to-on correspondence to each other, and a pair of the memory cell devices being in one-to-on correspondence to each other have one-side terminals electrically connected to each other to constitute one synapse morphic device. A plurality of the pairs of memory cell devices configured with the first and second cell strings constituting each synapse string constitute a plurality of the synapse morphic devices. The synapse morphic devices of each synapse string are electrically connected to the synapse morphic devices of other synapse strings.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: October 4, 2022
    Assignee: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Jong-Ho Lee, Sung-Tae Lee
  • Patent number: 11450679
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings and support openings are formed through the alternating stack, and memory opening fill structures and support pillar structures are formed in the memory openings and in the support openings, respectively. Via cavities extending to each of the sacrificial material layers are formed through the alternating stack without forming any stepped surfaces in the alternating stack. The via cavities may be formed in areas that do not overlap with the support pillar structures, or in areas that include at least one support pillar structure. Sacrificial via fill structures are formed in the via cavies, and the sacrificial material layers are replaced with electrically conductive layers. The sacrificial via fill structures are removed, and a combination of a tubular dielectric spacer and a contact via structure can be formed in the via cavities.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: September 20, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yoshinobu Tanaka, Koichi Ito, Hideaki Hasegawa, Akihiro Tobioka, Sung Tae Lee
  • Publication number: 20220005824
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings and support openings are formed through the alternating stack, and memory opening fill structures and support pillar structures are formed in the memory openings and in the support openings, respectively. Via cavities extending to each of the sacrificial material layers are formed through the alternating stack without forming any stepped surfaces in the alternating stack. The via cavities may be formed in areas that do not overlap with the support pillar structures, or in areas that include at least one support pillar structure. Sacrificial via fill structures are formed in the via cavies, and the sacrificial material layers are replaced with electrically conductive layers. The sacrificial via fill structures are removed, and a combination of a tubular dielectric spacer and a contact via structure can be formed in the via cavities.
    Type: Application
    Filed: July 1, 2020
    Publication date: January 6, 2022
    Inventors: Yoshinobu TANAKA, Koichi ITO, Hideaki HASEGAWA, Akihiro TOBIOKA, Sung Tae LEE
  • Publication number: 20220005818
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings and support openings are formed through the alternating stack, and memory opening fill structures and support pillar structures are formed in the memory openings and in the support openings, respectively. Via cavities extending to each of the sacrificial material layers are formed through the alternating stack without forming any stepped surfaces in the alternating stack. The via cavities may be formed in areas that do not overlap with the support pillar structures, or in areas that include at least one support pillar structure. Sacrificial via fill structures are formed in the via cavies, and the sacrificial material layers are replaced with electrically conductive layers. The sacrificial via fill structures are removed, and a combination of a tubular dielectric spacer and a contact via structure can be formed in the via cavities.
    Type: Application
    Filed: July 1, 2020
    Publication date: January 6, 2022
    Inventors: Yoshinobu TANAKA, Koichi ITO, Hideaki HASEGAWA, Akihiro TOBIOKA, Sung Tae LEE
  • Publication number: 20210209454
    Abstract: A synapse string includes first and second cell strings each having a plurality of memory cell elements connected in series and first switch elements connected to first or second ends of the first and second cell strings, respectively. The memory cell elements of the first cell string and the memory cell elements of the second cell string are in a one-to-one correspondence, and a pair of the memory cell elements being in a one-to-one correspondence has terminals to which a read voltage is applied connected to each other to constitute one synapse morphic element, so that the synapse string includes a plurality of synapse morphic elements connected in series. A synapse string array architecture enables forward propagation and backward propagation by implementing high-density synapse strings, so that the synapse string array architecture can be applied to a neural network capable of inferencing and on-chip learning, along with inference and recognition.
    Type: Application
    Filed: December 31, 2020
    Publication date: July 8, 2021
    Inventors: Jong-Ho LEE, Sung-Tae LEE
  • Publication number: 20210166108
    Abstract: Provided is a binary neural network including: a synapse string array in which multiple synapse strings are sequentially connected. The synapse string includes: first and second cell strings, each including memory cell devices connected in series; and switching devices connected to first ends of two-side ends of the first and second cell strings. The memory cell devices of the first and second cell strings are in one-to-on correspondence to each other, and a pair of the memory cell devices being in one-to-on correspondence to each other have one-side terminals electrically connected to each other to constitute one synapse morphic device. A plurality of the pairs of memory cell devices configured with the first and second cell strings constituting each synapse string constitute a plurality of the synapse morphic devices. The synapse morphic devices of each synapse string are electrically connected to the synapse morphic devices of other synapse strings.
    Type: Application
    Filed: March 16, 2020
    Publication date: June 3, 2021
    Inventors: Jong-Ho LEE, Sung-Tae Lee
  • Patent number: 10957396
    Abstract: Provided is synapse strings and synapse string arrays. The synapse string includes: first and second cell strings, each having a plurality of memory cell devices connected in series; and first switch devices, each connected to one of two ends of each of the first and second cell strings. The memory cell devices of the first cell string and the memory cell devices of the second cell string are in one-to-one correspondence to each other, and terminals of pairs of the memory cell devices being in one-to-one correspondence to each other are applied with read voltages and electrically connected to each other to constitute one synapse morphic device, so that the synapse string includes a plurality of synapse morphic devices connected in series. The synapse string includes a peripheral circuit and a reference current source for implementing a function of a neuron.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: March 23, 2021
    Assignee: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Jong-Ho Lee, Sung-Tae Lee
  • Patent number: 10847376
    Abstract: A first material layer, a second material layer, and a photoresist layer may be formed over a substrate. The second material layer may be patterned by transfer of a lithographic pattern therethrough. A conformal spacer layer may be formed over the patterned second material layer in a chamber enclosure of an in-situ deposition-etch apparatus. Spacer films may be formed by anisotropically etching the conformal spacer layer in the chamber enclosure of the in-situ deposition-etch apparatus. The first material layer may be anisotropically etched using a combination of the patterned second material layer and the spacer films as an etch mask in the in-situ deposition-etch apparatus. A high fidelity pattern may be transferred into the first material layer with reduced line edge roughness, reduced line width roughness, and without enlargement of lateral dimensions of openings in the first material layer.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: November 24, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yusuke Osawa, Syo Fukata, Naoto Umehara, Sung Tae Lee
  • Publication number: 20200294602
    Abstract: Provided is synapse strings and synapse string arrays. The synapse string includes: first and second cell strings, each having a plurality of memory cell devices connected in series; and first switch devices, each connected to one of two ends of each of the first and second cell strings. The memory cell devices of the first cell string and the memory cell devices of the second cell string are in one-to-one correspondence to each other, and terminals of pairs of the memory cell devices being in one-to-one correspondence to each other are applied with read voltages and electrically connected to each other to constitute one synapse morphic device, so that the synapse string includes a plurality of synapse morphic devices connected in series. The synapse string includes a peripheral circuit and a reference current source for implementing a function of a neuron.
    Type: Application
    Filed: March 11, 2020
    Publication date: September 17, 2020
    Inventors: Jong-Ho LEE, Sung-Tae LEE
  • Publication number: 20200006080
    Abstract: A first material layer, a second material layer, and a photoresist layer may be formed over a substrate. The second material layer may be patterned by transfer of a lithographic pattern therethrough. A conformal spacer layer may be formed over the patterned second material layer in a chamber enclosure of an in-situ deposition-etch apparatus. Spacer films may be formed by anisotropically etching the conformal spacer layer in the chamber enclosure of the in-situ deposition-etch apparatus. The first material layer may be anisotropically etched using a combination of the patterned second material layer and the spacer films as an etch mask in the in-situ deposition-etch apparatus. A high fidelity pattern may be transferred into the first material layer with reduced line edge roughness, reduced line width roughness, and without enlargement of lateral dimensions of openings in the first material layer.
    Type: Application
    Filed: April 10, 2019
    Publication date: January 2, 2020
    Inventors: Yusuke OSAWA, Syo FUKATA, Naoto UMEHARA, Sung Tae LEE
  • Patent number: 10325713
    Abstract: An inductor includes a support having first and second coils formed on first and second surfaces thereof, respectively; a body embedding the support therein so that end portions of the first and second coils are exposed through first and second surfaces of the body opposing each other, and including a first magnetic part disposed in cores of the first and second coils and on upper and lower surfaces of the first and second coils, respectively, and second magnetic parts disposed on upper and lower surfaces of the first magnetic part, respectively; and first and second external electrodes formed on outer surfaces of the body to be electrically connected to the end portions of the first and second coils, respectively. The second magnetic part has a content of a hardening accelerator greater than that of the first magnetic part.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: June 18, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jeong Hyun Park, Sung Tae Lee
  • Patent number: 10269620
    Abstract: Contacts to peripheral devices extending through multiple tier structures of a three-dimensional memory device can be formed with minimal additional processing steps. First peripheral via cavities through a first tier structure can be formed concurrently with formation of first memory openings. Sacrificial via fill structures can be formed in the first peripheral via cavities concurrently with formation of sacrificial memory opening fill structures that are formed in the first memory openings. Second peripheral via cavities through a second tier structure can be formed concurrently with formation of word line contact via cavities that extend to top surfaces of electrically conductive layers in the first and second tier structures. After removal of the sacrificial via fill structures, the first and second peripheral via cavities can be filled with a conductive material to form peripheral contact via structures concurrently with formation of word line contact via structures.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: April 23, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Jixin Yu, Zhenyu Lu, Hiroyuki Ogawa, Daxin Mao, Kensuke Yamaguchi, Sung Tae Lee, Yao-sheng Lee, Johann Alsmeier
  • Publication number: 20170309388
    Abstract: An inductor includes a support having first and second coils formed on first and second surfaces thereof, respectively; a body embedding the support therein so that end portions of the first and second coils are exposed through first and second surfaces of the body opposing each other, and including a first magnetic part disposed in cores of the first and second coils and on upper and lower surfaces of the first and second coils, respectively, and second magnetic parts disposed on upper and lower surfaces of the first magnetic part, respectively; and first and second external electrodes formed on outer surfaces of the body to be electrically connected to the end portions of the first and second coils, respectively. The second magnetic part has a content of a hardening accelerator greater than that of the first magnetic part.
    Type: Application
    Filed: February 15, 2017
    Publication date: October 26, 2017
    Inventors: Jeong Hyun PARK, Sung Tae LEE
  • Publication number: 20170236746
    Abstract: Contacts to peripheral devices extending through multiple tier structures of a three-dimensional memory device can be formed with minimal additional processing steps. First peripheral via cavities through a first tier structure can be formed concurrently with formation of first memory openings. Sacrificial via fill structures can be formed in the first peripheral via cavities concurrently with formation of sacrificial memory opening fill structures that are formed in the first memory openings. Second peripheral via cavities through a second tier structure can be formed concurrently with formation of word line contact via cavities that extend to top surfaces of electrically conductive layers in the first and second tier structures. After removal of the sacrificial via fill structures, the first and second peripheral via cavities can be filled with a conductive material to form peripheral contact via structures concurrently with formation of word line contact via structures.
    Type: Application
    Filed: September 23, 2016
    Publication date: August 17, 2017
    Inventors: Jixin YU, Zhenyu LU, Hiroyuki OGAWA, Daxin MAO, Kensuke YAMAGUCHI, Sung Tae LEE, Yao-sheng LEE, Johann ALSMEIER
  • Patent number: 9673304
    Abstract: A method is provided that includes forming a dielectric material above a substrate, forming a hole in the dielectric material, the hole disposed in a first direction, forming a word line layer above the substrate via the hole, the word line layer disposed in a second direction perpendicular to the first direction, forming a nonvolatile memory material on a sidewall of the hole, forming a local bit line in the hole, and forming a memory cell including the nonvolatile memory material at an intersection of the local bit line and the word line layer.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: June 6, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Michiaki Sano, Akira Nakada, Tetsuya Yamada, Manabu Hayashi, Takashi Matsubara, Sung Tae Lee, Akio Nishida
  • Patent number: 9437543
    Abstract: A contact via cavity can be filled with a lower structure and an upper structure. The lower structure can be a conductive structure that is formed by depositing a conformal conductive material, and subsequently removing an upper portion of the conformal conductive material. A disposable material portion can be formed at a bottom of the cavity to protect the bottom portion of the conformal conductive layer during removal of the upper portion. After removal of the disposable material, at least one conductive material can fill the remainder of the cavity to form the upper structure. The upper structure and the lower structure collectively constitute a contact via structure. Alternatively, the lower structure can be a dielectric spacer with an opening therethrough. The upper structure can be a conductive structure that extends through the dielectric spacer, and provides an electrically conductive vertical connection.
    Type: Grant
    Filed: January 22, 2015
    Date of Patent: September 6, 2016
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Akira Nakada, Michiaki Sano, Motoki Kawasaki, Sung Tae Lee
  • Patent number: D887071
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: June 9, 2020
    Assignee: LG Display Co., Ltd.
    Inventors: Hye Cho Shin, Jeong Ho Son, Hyun Soo Chung, Ah Ra Cho, Chi Young Lee, Duck Su Oh, Sung Tae Lee, Ho Geol Lim
  • Patent number: D930873
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: September 14, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Hye Cho Shin, Jeong Ho Son, Hyun Soo Chung, Ah Ra Cho, Chi Young Lee, Duck Su Oh, Sung Tae Lee, Ho Geol Lim