Patents by Inventor Sung Tae Lee
Sung Tae Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11928579Abstract: A synapse string includes first and second cell strings each having a plurality of memory cell elements connected in series and first switch elements connected to first or second ends of the first and second cell strings, respectively. The memory cell elements of the first cell string and the memory cell elements of the second cell string are in a one-to-one correspondence, and a pair of the memory cell elements being in a one-to-one correspondence has terminals to which a read voltage is applied connected to each other to constitute one synapse morphic element, so that the synapse string includes a plurality of synapse morphic elements connected in series. A synapse string array architecture enables forward propagation and backward propagation by implementing high-density synapse strings, so that the synapse string array architecture can be applied to a neural network capable of inferencing and on-chip learning, along with inference and recognition.Type: GrantFiled: December 31, 2020Date of Patent: March 12, 2024Assignee: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATIONInventors: Jong-Ho Lee, Sung-Tae Lee
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Patent number: 11495612Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings and support openings are formed through the alternating stack, and memory opening fill structures and support pillar structures are formed in the memory openings and in the support openings, respectively. Via cavities extending to each of the sacrificial material layers are formed through the alternating stack without forming any stepped surfaces in the alternating stack. The via cavities may be formed in areas that do not overlap with the support pillar structures, or in areas that include at least one support pillar structure. Sacrificial via fill structures are formed in the via cavies, and the sacrificial material layers are replaced with electrically conductive layers. The sacrificial via fill structures are removed, and a combination of a tubular dielectric spacer and a contact via structure can be formed in the via cavities.Type: GrantFiled: July 1, 2020Date of Patent: November 8, 2022Assignee: SANDISK TECHNOLOGIES LLCInventors: Yoshinobu Tanaka, Koichi Ito, Hideaki Hasegawa, Akihiro Tobioka, Sung Tae Lee
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Patent number: 11461624Abstract: Provided is a binary neural network including: a synapse string array in which multiple synapse strings are sequentially connected. The synapse string includes: first and second cell strings, each including memory cell devices connected in series; and switching devices connected to first ends of two-side ends of the first and second cell strings. The memory cell devices of the first and second cell strings are in one-to-on correspondence to each other, and a pair of the memory cell devices being in one-to-on correspondence to each other have one-side terminals electrically connected to each other to constitute one synapse morphic device. A plurality of the pairs of memory cell devices configured with the first and second cell strings constituting each synapse string constitute a plurality of the synapse morphic devices. The synapse morphic devices of each synapse string are electrically connected to the synapse morphic devices of other synapse strings.Type: GrantFiled: March 16, 2020Date of Patent: October 4, 2022Assignee: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATIONInventors: Jong-Ho Lee, Sung-Tae Lee
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Patent number: 11450679Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings and support openings are formed through the alternating stack, and memory opening fill structures and support pillar structures are formed in the memory openings and in the support openings, respectively. Via cavities extending to each of the sacrificial material layers are formed through the alternating stack without forming any stepped surfaces in the alternating stack. The via cavities may be formed in areas that do not overlap with the support pillar structures, or in areas that include at least one support pillar structure. Sacrificial via fill structures are formed in the via cavies, and the sacrificial material layers are replaced with electrically conductive layers. The sacrificial via fill structures are removed, and a combination of a tubular dielectric spacer and a contact via structure can be formed in the via cavities.Type: GrantFiled: July 1, 2020Date of Patent: September 20, 2022Assignee: SANDISK TECHNOLOGIES LLCInventors: Yoshinobu Tanaka, Koichi Ito, Hideaki Hasegawa, Akihiro Tobioka, Sung Tae Lee
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Publication number: 20220005824Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings and support openings are formed through the alternating stack, and memory opening fill structures and support pillar structures are formed in the memory openings and in the support openings, respectively. Via cavities extending to each of the sacrificial material layers are formed through the alternating stack without forming any stepped surfaces in the alternating stack. The via cavities may be formed in areas that do not overlap with the support pillar structures, or in areas that include at least one support pillar structure. Sacrificial via fill structures are formed in the via cavies, and the sacrificial material layers are replaced with electrically conductive layers. The sacrificial via fill structures are removed, and a combination of a tubular dielectric spacer and a contact via structure can be formed in the via cavities.Type: ApplicationFiled: July 1, 2020Publication date: January 6, 2022Inventors: Yoshinobu TANAKA, Koichi ITO, Hideaki HASEGAWA, Akihiro TOBIOKA, Sung Tae LEE
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Publication number: 20220005818Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings and support openings are formed through the alternating stack, and memory opening fill structures and support pillar structures are formed in the memory openings and in the support openings, respectively. Via cavities extending to each of the sacrificial material layers are formed through the alternating stack without forming any stepped surfaces in the alternating stack. The via cavities may be formed in areas that do not overlap with the support pillar structures, or in areas that include at least one support pillar structure. Sacrificial via fill structures are formed in the via cavies, and the sacrificial material layers are replaced with electrically conductive layers. The sacrificial via fill structures are removed, and a combination of a tubular dielectric spacer and a contact via structure can be formed in the via cavities.Type: ApplicationFiled: July 1, 2020Publication date: January 6, 2022Inventors: Yoshinobu TANAKA, Koichi ITO, Hideaki HASEGAWA, Akihiro TOBIOKA, Sung Tae LEE
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Publication number: 20210209454Abstract: A synapse string includes first and second cell strings each having a plurality of memory cell elements connected in series and first switch elements connected to first or second ends of the first and second cell strings, respectively. The memory cell elements of the first cell string and the memory cell elements of the second cell string are in a one-to-one correspondence, and a pair of the memory cell elements being in a one-to-one correspondence has terminals to which a read voltage is applied connected to each other to constitute one synapse morphic element, so that the synapse string includes a plurality of synapse morphic elements connected in series. A synapse string array architecture enables forward propagation and backward propagation by implementing high-density synapse strings, so that the synapse string array architecture can be applied to a neural network capable of inferencing and on-chip learning, along with inference and recognition.Type: ApplicationFiled: December 31, 2020Publication date: July 8, 2021Inventors: Jong-Ho LEE, Sung-Tae LEE
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Publication number: 20210166108Abstract: Provided is a binary neural network including: a synapse string array in which multiple synapse strings are sequentially connected. The synapse string includes: first and second cell strings, each including memory cell devices connected in series; and switching devices connected to first ends of two-side ends of the first and second cell strings. The memory cell devices of the first and second cell strings are in one-to-on correspondence to each other, and a pair of the memory cell devices being in one-to-on correspondence to each other have one-side terminals electrically connected to each other to constitute one synapse morphic device. A plurality of the pairs of memory cell devices configured with the first and second cell strings constituting each synapse string constitute a plurality of the synapse morphic devices. The synapse morphic devices of each synapse string are electrically connected to the synapse morphic devices of other synapse strings.Type: ApplicationFiled: March 16, 2020Publication date: June 3, 2021Inventors: Jong-Ho LEE, Sung-Tae Lee
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Patent number: 10957396Abstract: Provided is synapse strings and synapse string arrays. The synapse string includes: first and second cell strings, each having a plurality of memory cell devices connected in series; and first switch devices, each connected to one of two ends of each of the first and second cell strings. The memory cell devices of the first cell string and the memory cell devices of the second cell string are in one-to-one correspondence to each other, and terminals of pairs of the memory cell devices being in one-to-one correspondence to each other are applied with read voltages and electrically connected to each other to constitute one synapse morphic device, so that the synapse string includes a plurality of synapse morphic devices connected in series. The synapse string includes a peripheral circuit and a reference current source for implementing a function of a neuron.Type: GrantFiled: March 11, 2020Date of Patent: March 23, 2021Assignee: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATIONInventors: Jong-Ho Lee, Sung-Tae Lee
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Patent number: 10847376Abstract: A first material layer, a second material layer, and a photoresist layer may be formed over a substrate. The second material layer may be patterned by transfer of a lithographic pattern therethrough. A conformal spacer layer may be formed over the patterned second material layer in a chamber enclosure of an in-situ deposition-etch apparatus. Spacer films may be formed by anisotropically etching the conformal spacer layer in the chamber enclosure of the in-situ deposition-etch apparatus. The first material layer may be anisotropically etched using a combination of the patterned second material layer and the spacer films as an etch mask in the in-situ deposition-etch apparatus. A high fidelity pattern may be transferred into the first material layer with reduced line edge roughness, reduced line width roughness, and without enlargement of lateral dimensions of openings in the first material layer.Type: GrantFiled: April 10, 2019Date of Patent: November 24, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Yusuke Osawa, Syo Fukata, Naoto Umehara, Sung Tae Lee
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Publication number: 20200294602Abstract: Provided is synapse strings and synapse string arrays. The synapse string includes: first and second cell strings, each having a plurality of memory cell devices connected in series; and first switch devices, each connected to one of two ends of each of the first and second cell strings. The memory cell devices of the first cell string and the memory cell devices of the second cell string are in one-to-one correspondence to each other, and terminals of pairs of the memory cell devices being in one-to-one correspondence to each other are applied with read voltages and electrically connected to each other to constitute one synapse morphic device, so that the synapse string includes a plurality of synapse morphic devices connected in series. The synapse string includes a peripheral circuit and a reference current source for implementing a function of a neuron.Type: ApplicationFiled: March 11, 2020Publication date: September 17, 2020Inventors: Jong-Ho LEE, Sung-Tae LEE
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Publication number: 20200006080Abstract: A first material layer, a second material layer, and a photoresist layer may be formed over a substrate. The second material layer may be patterned by transfer of a lithographic pattern therethrough. A conformal spacer layer may be formed over the patterned second material layer in a chamber enclosure of an in-situ deposition-etch apparatus. Spacer films may be formed by anisotropically etching the conformal spacer layer in the chamber enclosure of the in-situ deposition-etch apparatus. The first material layer may be anisotropically etched using a combination of the patterned second material layer and the spacer films as an etch mask in the in-situ deposition-etch apparatus. A high fidelity pattern may be transferred into the first material layer with reduced line edge roughness, reduced line width roughness, and without enlargement of lateral dimensions of openings in the first material layer.Type: ApplicationFiled: April 10, 2019Publication date: January 2, 2020Inventors: Yusuke OSAWA, Syo FUKATA, Naoto UMEHARA, Sung Tae LEE
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Patent number: 10325713Abstract: An inductor includes a support having first and second coils formed on first and second surfaces thereof, respectively; a body embedding the support therein so that end portions of the first and second coils are exposed through first and second surfaces of the body opposing each other, and including a first magnetic part disposed in cores of the first and second coils and on upper and lower surfaces of the first and second coils, respectively, and second magnetic parts disposed on upper and lower surfaces of the first magnetic part, respectively; and first and second external electrodes formed on outer surfaces of the body to be electrically connected to the end portions of the first and second coils, respectively. The second magnetic part has a content of a hardening accelerator greater than that of the first magnetic part.Type: GrantFiled: February 15, 2017Date of Patent: June 18, 2019Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Jeong Hyun Park, Sung Tae Lee
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Patent number: 10269620Abstract: Contacts to peripheral devices extending through multiple tier structures of a three-dimensional memory device can be formed with minimal additional processing steps. First peripheral via cavities through a first tier structure can be formed concurrently with formation of first memory openings. Sacrificial via fill structures can be formed in the first peripheral via cavities concurrently with formation of sacrificial memory opening fill structures that are formed in the first memory openings. Second peripheral via cavities through a second tier structure can be formed concurrently with formation of word line contact via cavities that extend to top surfaces of electrically conductive layers in the first and second tier structures. After removal of the sacrificial via fill structures, the first and second peripheral via cavities can be filled with a conductive material to form peripheral contact via structures concurrently with formation of word line contact via structures.Type: GrantFiled: September 23, 2016Date of Patent: April 23, 2019Assignee: SANDISK TECHNOLOGIES LLCInventors: Jixin Yu, Zhenyu Lu, Hiroyuki Ogawa, Daxin Mao, Kensuke Yamaguchi, Sung Tae Lee, Yao-sheng Lee, Johann Alsmeier
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Publication number: 20170309388Abstract: An inductor includes a support having first and second coils formed on first and second surfaces thereof, respectively; a body embedding the support therein so that end portions of the first and second coils are exposed through first and second surfaces of the body opposing each other, and including a first magnetic part disposed in cores of the first and second coils and on upper and lower surfaces of the first and second coils, respectively, and second magnetic parts disposed on upper and lower surfaces of the first magnetic part, respectively; and first and second external electrodes formed on outer surfaces of the body to be electrically connected to the end portions of the first and second coils, respectively. The second magnetic part has a content of a hardening accelerator greater than that of the first magnetic part.Type: ApplicationFiled: February 15, 2017Publication date: October 26, 2017Inventors: Jeong Hyun PARK, Sung Tae LEE
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Publication number: 20170236746Abstract: Contacts to peripheral devices extending through multiple tier structures of a three-dimensional memory device can be formed with minimal additional processing steps. First peripheral via cavities through a first tier structure can be formed concurrently with formation of first memory openings. Sacrificial via fill structures can be formed in the first peripheral via cavities concurrently with formation of sacrificial memory opening fill structures that are formed in the first memory openings. Second peripheral via cavities through a second tier structure can be formed concurrently with formation of word line contact via cavities that extend to top surfaces of electrically conductive layers in the first and second tier structures. After removal of the sacrificial via fill structures, the first and second peripheral via cavities can be filled with a conductive material to form peripheral contact via structures concurrently with formation of word line contact via structures.Type: ApplicationFiled: September 23, 2016Publication date: August 17, 2017Inventors: Jixin YU, Zhenyu LU, Hiroyuki OGAWA, Daxin MAO, Kensuke YAMAGUCHI, Sung Tae LEE, Yao-sheng LEE, Johann ALSMEIER
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Patent number: 9673304Abstract: A method is provided that includes forming a dielectric material above a substrate, forming a hole in the dielectric material, the hole disposed in a first direction, forming a word line layer above the substrate via the hole, the word line layer disposed in a second direction perpendicular to the first direction, forming a nonvolatile memory material on a sidewall of the hole, forming a local bit line in the hole, and forming a memory cell including the nonvolatile memory material at an intersection of the local bit line and the word line layer.Type: GrantFiled: July 15, 2016Date of Patent: June 6, 2017Assignee: SanDisk Technologies LLCInventors: Michiaki Sano, Akira Nakada, Tetsuya Yamada, Manabu Hayashi, Takashi Matsubara, Sung Tae Lee, Akio Nishida
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Patent number: 9437543Abstract: A contact via cavity can be filled with a lower structure and an upper structure. The lower structure can be a conductive structure that is formed by depositing a conformal conductive material, and subsequently removing an upper portion of the conformal conductive material. A disposable material portion can be formed at a bottom of the cavity to protect the bottom portion of the conformal conductive layer during removal of the upper portion. After removal of the disposable material, at least one conductive material can fill the remainder of the cavity to form the upper structure. The upper structure and the lower structure collectively constitute a contact via structure. Alternatively, the lower structure can be a dielectric spacer with an opening therethrough. The upper structure can be a conductive structure that extends through the dielectric spacer, and provides an electrically conductive vertical connection.Type: GrantFiled: January 22, 2015Date of Patent: September 6, 2016Assignee: SANDISK TECHNOLOGIES LLCInventors: Akira Nakada, Michiaki Sano, Motoki Kawasaki, Sung Tae Lee
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Patent number: D887071Type: GrantFiled: July 19, 2018Date of Patent: June 9, 2020Assignee: LG Display Co., Ltd.Inventors: Hye Cho Shin, Jeong Ho Son, Hyun Soo Chung, Ah Ra Cho, Chi Young Lee, Duck Su Oh, Sung Tae Lee, Ho Geol Lim
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Patent number: D930873Type: GrantFiled: July 19, 2018Date of Patent: September 14, 2021Assignee: LG DISPLAY CO., LTD.Inventors: Hye Cho Shin, Jeong Ho Son, Hyun Soo Chung, Ah Ra Cho, Chi Young Lee, Duck Su Oh, Sung Tae Lee, Ho Geol Lim