Patents by Inventor Sunit Tyagi

Sunit Tyagi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190265387
    Abstract: Surface modification control stations and methods in a globally distributed array for dynamically adjusting the atmospheric, terrestrial and oceanic properties. The control stations modify the humidity, currents, wind flows and heat removal rate of the surface and facilitate cooling and control of large area of global surface temperatures. This global system is made of arrays of multiple sub-systems that monitor climate and act locally on weather with dynamically generated local forcing & perturbations for guiding in a controlled manner aim at long-term modifications. The machineries are part of a large-scale system consisting of an array of many such machines put across the globe at locations called the control stations. These are then used in a coordinated manner to modify large area weather and the global climate as desired.
    Type: Application
    Filed: May 10, 2019
    Publication date: August 29, 2019
    Inventor: Sunit Tyagi
  • Publication number: 20180102646
    Abstract: Disclosed examples relate to a power conversion system configured to provide a power output from an arrangement of direct current (DC) power sources. One example power conversion system includes multiple power sources PV(n), n=1 to x, connected in a series. For each power source PV(n) for n=1 to x?1, the power conversion system includes an intermediate bidirectional voltage converter VC(n) connected to a first terminal of the power source PV(n), a first terminal of power source PV(x), and a second terminal of power source PV(1). Each intermediate bidirectional voltage converter VC(n) includes a first switch operable in a pulsed mode to boost a power output by power source PV(n) and a second switch operable in a pulsed mode to reduce a power output by power source PV(n). The power conversion system also includes a balancer VC(x) connected to the first terminal of PV(x) and to a load.
    Type: Application
    Filed: October 10, 2017
    Publication date: April 12, 2018
    Inventors: Jitendra Apte, Alok Srivastava, Hemanshu Bhatt, Sunit Tyagi, Dipti Kapadia, Vinod Kumar Singh, Bhawani Patnaik, Leah Mathew
  • Patent number: 9577548
    Abstract: Embodiments related to the conversion of DC power to AC power are disclosed. For example, one disclosed embodiment provides a power conversion system, comprising a plurality of direct current (DC) power sources, a plurality of power output circuits connected to one another in a parallel arrangement, each power output circuit being connected to a corresponding DC power source to receive power from the corresponding DC power source and to selectively discharge power received from the corresponding DC power source, a power combiner configured to combine power received from the plurality of power output circuits to form a combined power signal, an output stage configured to convert the combined power signal into an AC signal or a DC signal, and a controller in electrical communication with each power outlet circuit and the power combiner to control the output of power by the power converter.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: February 21, 2017
    Assignee: IgrenEnergi, Inc.
    Inventors: Sunit Tyagi, Hemanshu Bhatt
  • Publication number: 20140008987
    Abstract: Embodiments related to the conversion of DC power to AC power are disclosed. For example, one disclosed embodiment provides a power conversion system, comprising a plurality of direct current (DC) power sources, a plurality of power output circuits connected to one another in a parallel arrangement, each power output circuit being connected to a corresponding DC power source to receive power from the corresponding DC power source and to selectively discharge power received from the corresponding DC power source, a power combiner configured to combine power received from the plurality of power output circuits to form a combined power signal, an output stage configured to convert the combined power signal into an AC signal or a DC signal, and a controller in electrical communication with each power outlet circuit and the power combiner to control the output of power by the power converter.
    Type: Application
    Filed: September 3, 2013
    Publication date: January 9, 2014
    Applicant: igrenEnergi Semiconductor Technologies Pvt. Ltd.
    Inventors: Sunit Tyagi, Hemanshu Bhatt
  • Patent number: 8552587
    Abstract: Embodiments related to the conversion of DC power to AC power are disclosed. For example, one disclosed embodiment provides a power conversion system, comprising a plurality of direct current (DC) power sources, a plurality of power output circuits connected to one another in a parallel arrangement, each power output circuit being connected to a corresponding DC power source to receive power from the corresponding DC power source and to selectively discharge power received from the corresponding DC power source, a power combiner configured to combine power received from the plurality of power output circuits to form a combined power signal, an output stage configured to convert the combined power signal into an AC signal or a DC signal, and a controller in electrical communication with each power outlet circuit and the power combiner to control the output of power by the power converter.
    Type: Grant
    Filed: July 20, 2010
    Date of Patent: October 8, 2013
    Assignee: igrenEnergi Semiconductor Technologies Pvt. Ltd.
    Inventors: Sunit Tyagi, Hemanshu Bhatt
  • Publication number: 20120019072
    Abstract: Embodiments related to the conversion of DC power to AC power are disclosed. For example, one disclosed embodiment provides a power conversion system, comprising a plurality of direct current (DC) power sources, a plurality of power output circuits connected to one another in a parallel arrangement, each power output circuit being connected to a corresponding DC power source to receive power from the corresponding DC power source and to selectively discharge power received from the corresponding DC power source, a power combiner configured to combine power received from the plurality of power output circuits to form a combined power signal, an output stage configured to convert the combined power signal into an AC signal or a DC signal, and a controller in electrical communication with each power outlet circuit and the power combiner to control the output of power by the power converter.
    Type: Application
    Filed: July 20, 2010
    Publication date: January 26, 2012
    Applicant: INSOLARE ENERGY PRIVATE LIMITED
    Inventors: Sunit Tyagi, Hemanshu Bhatt
  • Patent number: 7888710
    Abstract: Complementary metal oxide semiconductor transistors are formed on a silicon substrate. The substrate has a {100} crystallographic orientation. The transistors are formed on the substrate so that current flows in the channels of the transistors are parallel to the <100> direction. Additionally, longitudinal tensile stress is applied to the channels.
    Type: Grant
    Filed: October 17, 2007
    Date of Patent: February 15, 2011
    Assignee: Intel Corporation
    Inventors: Mark Armstrong, Gerhard Schrom, Sunit Tyagi, Paul A. Packan, Kelin J. Kuhn, Scott Thompson
  • Patent number: 7581154
    Abstract: A method comprising running an error correction code on data and storing the data and the result of the error correction code in memory, running an error correction code on the data when it is read from the memory, comparing the results of the error correction codes on the data from before and after the memory, correcting errors when the comparator determines a difference in the results of the error correction codes and lowering the operating voltage of the memory array while using the error correction.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: August 25, 2009
    Assignee: Intel Corporation
    Inventors: Nivruti Rai, Anshumali Kumar, Edward Burton, Sunit Tyagi, Jeffrey L. Miller
  • Patent number: 7560780
    Abstract: A semiconductor device and method for its fabrication are described. An active region spacer may be formed on a top surface of an isolation region and adjacent to a sidewall of an active region. In one embodiment, the active region spacer may suppress the formation of metal pipes in the active region.
    Type: Grant
    Filed: December 8, 2005
    Date of Patent: July 14, 2009
    Assignee: Intel Corporation
    Inventors: Giuseppe Curello, Ian R. Post, Chia-Hong Jan, Sunit Tyagi, Mark Bohr
  • Patent number: 7473591
    Abstract: Various methods for forming a layer of strained silicon in a channel region of a device and devices constructed according to the disclosed methods. In one embodiment, a strain-inducing layer is formed, a relaxed layer is formed on the strain-inducing layer, a portion of the strain-inducing layer is removed, which allows the strain-inducing layer to relax and strain the relaxed layer.
    Type: Grant
    Filed: December 1, 2005
    Date of Patent: January 6, 2009
    Assignee: Intel Corporation
    Inventors: Stephen M. Cea, Ravindra Soman, Ramune Nagisetty, Sunit Tyagi, Sanjay Natarajan
  • Publication number: 20080311720
    Abstract: A method of forming a transistor comprising: defining undercut recesses in the substrate at the source/drain regions thereof, the undercut recesses extending beneath the gate electrode; creating a halo implant region beneath the gate electrode between the recesses; and providing raised source/drain structures in the undercut recesses after creating the halo implant region.
    Type: Application
    Filed: July 11, 2008
    Publication date: December 18, 2008
    Inventors: Thomas Hoffman, Sunit Tyagi, Giuseppe Curello, Berhard Sell, Christopher Auth
  • Patent number: 7422950
    Abstract: A MOS device comprises a gate stack comprising a gate electrode disposed on a gate dielectric, a first spacer and a second spacer formed on laterally opposite sides of the gate stack, a source region proximate to the first spacer, a drain region proximate to the second spacer, and a channel region subjacent to the gate stack and disposed between the source region and the drain region. The MOS device of the invention further includes a buried oxide (BOX) region subjacent to the channel region and disposed between the source region and the drain region. The BOX region enables deeper source and drain regions to be formed to reduce transistor resistance and silicide spike defects while preventing gate edge junction parasitic capacitance.
    Type: Grant
    Filed: December 14, 2005
    Date of Patent: September 9, 2008
    Assignee: Intel Corporation
    Inventors: Giuseppe Curello, Hemant V. Deshpande, Sunit Tyagi, Mark Bohr
  • Patent number: 7335959
    Abstract: Embodiments of the invention provide a transistor with stepped source and drain regions. The stepped regions may provide significant strain in a channel region while minimizing current leakage. The stepped regions may be formed by forming two recesses in a substrate to result in a stepped recess, and forming the source/drain regions in the recesses.
    Type: Grant
    Filed: January 6, 2005
    Date of Patent: February 26, 2008
    Assignee: Intel Corporation
    Inventors: Giuseppe Curello, Bernhard Sell, Sunit Tyagi, Chris Auth
  • Publication number: 20080036005
    Abstract: Complementary metal oxide semiconductor transistors are formed on a silicon substrate. The substrate has a {100} crystallographic orientation. The transistors are formed on the substrate so that current flows in the channels of the transistors are parallel to the <100> direction. Additionally, longitudinal tensile stress is applied to the channels.
    Type: Application
    Filed: October 17, 2007
    Publication date: February 14, 2008
    Inventors: Mark Armstrong, Gerhard Schrom, Sunit Tyagi, Paul Packan, Kelin Kuhn, Scott Thompson
  • Patent number: 7312485
    Abstract: Complementary metal oxide semiconductor transistors are formed on a silicon substrate. The substrate has a {100} crystallographic orientation. The transistors are formed on the substrate so that current flows in the channels of the transistors are parallel to the <100> direction. Additionally, longitudinal tensile stress is applied to the channels.
    Type: Grant
    Filed: November 29, 2000
    Date of Patent: December 25, 2007
    Assignee: Intel Corporation
    Inventors: Mark Armstrong, Gerhard Schrom, Sunit Tyagi, Paul A. Packan, Kelin J. Kuhn, Scott Thompson
  • Publication number: 20070145495
    Abstract: A method including forming a transistor structure structure comprising a gate electrode over an active region of a substrate, the active region defined by a trench isolation structure and changing a performance of a narrow width transistor with respect to a wide width transistor by introducing a dopant into the active region adjacent an interface defined by the trench isolation structure and the gate electrode. A structure including a gate electrode formed on a substrate, an active region adjacent an interface defined by a trench isolation structure and a gate electrode and an implant within the active region to change a performance of a transistor.
    Type: Application
    Filed: December 27, 2005
    Publication date: June 28, 2007
    Inventors: Giuseppe Curello, Sivakumar Mudanai, Nick Lindert, Leonard Pipes, M. Shaheed, Sunit Tyagi
  • Publication number: 20070132057
    Abstract: A semiconductor device and method for its fabrication are described. An active region spacer may be formed on a top surface of an isolation region and adjacent to a sidewall of an active region. In one embodiment, the active region spacer may suppress the formation of metal pipes in the active region.
    Type: Application
    Filed: December 8, 2005
    Publication date: June 14, 2007
    Inventors: Giuseppe Curello, Ian Post, Chia-Hong Jan, Sunit Tyagi, Mark Bohr
  • Publication number: 20070132034
    Abstract: A semiconductor device and method for its fabrication are described. An isolation body may be formed prior to formation of an active region. In one embodiment, the isolation body is void-free.
    Type: Application
    Filed: December 14, 2005
    Publication date: June 14, 2007
    Inventors: Giuseppe Curello, Mark Bohr, Hemant Deshpande, Sunit Tyagi
  • Publication number: 20070134859
    Abstract: A MOS device comprises a gate stack comprising a gate electrode disposed on a gate dielectric, a first spacer and a second spacer formed on laterally opposite sides of the gate stack, a source region proximate to the first spacer, a drain region proximate to the second spacer, and a channel region subjacent to the gate stack and disposed between the source region and the drain region. The MOS device of the invention further includes a buried oxide (BOX) region subjacent to the channel region and disposed between the source region and the drain region. The BOX region enables deeper source and drain regions to be formed to reduce transistor resistance and silicide spike defects while preventing gate edge junction parasitic capacitance.
    Type: Application
    Filed: December 14, 2005
    Publication date: June 14, 2007
    Inventors: Giuseppe Curello, Hemant Deshpande, Sunit Tyagi, Mark Bohr
  • Publication number: 20070022360
    Abstract: A method comprising running an error correction code on data and storing the data and the result of the error correction code in memory, running an error correction code on the data when it is read from the memory, comparing the results of the error correction codes on the data from before and after the memory, correcting errors when the comparator determines a difference in the results of the error correction codes and lowering the operating voltage of the memory array while using the error correction.
    Type: Application
    Filed: June 30, 2005
    Publication date: January 25, 2007
    Inventors: Nivruti Rai, Anshumali Kumar, Edward Burton, Sunit Tyagi, Jeffrey Miller