Patents by Inventor Sunit Tyagi

Sunit Tyagi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070134859
    Abstract: A MOS device comprises a gate stack comprising a gate electrode disposed on a gate dielectric, a first spacer and a second spacer formed on laterally opposite sides of the gate stack, a source region proximate to the first spacer, a drain region proximate to the second spacer, and a channel region subjacent to the gate stack and disposed between the source region and the drain region. The MOS device of the invention further includes a buried oxide (BOX) region subjacent to the channel region and disposed between the source region and the drain region. The BOX region enables deeper source and drain regions to be formed to reduce transistor resistance and silicide spike defects while preventing gate edge junction parasitic capacitance.
    Type: Application
    Filed: December 14, 2005
    Publication date: June 14, 2007
    Inventors: Giuseppe Curello, Hemant Deshpande, Sunit Tyagi, Mark Bohr
  • Publication number: 20070022360
    Abstract: A method comprising running an error correction code on data and storing the data and the result of the error correction code in memory, running an error correction code on the data when it is read from the memory, comparing the results of the error correction codes on the data from before and after the memory, correcting errors when the comparator determines a difference in the results of the error correction codes and lowering the operating voltage of the memory array while using the error correction.
    Type: Application
    Filed: June 30, 2005
    Publication date: January 25, 2007
    Inventors: Nivruti Rai, Anshumali Kumar, Edward Burton, Sunit Tyagi, Jeffrey Miller
  • Publication number: 20070004114
    Abstract: A process for fabricating an n channel transistor, which results in electron mobility improvement in the channel, is described. Sacrificial capping layers comprising an oxide and nitride layer are conformally formed over a polysilicon gate after source and drain implantation, and remain in place during annealing.
    Type: Application
    Filed: June 30, 2005
    Publication date: January 4, 2007
    Inventors: Seok-Hee Lee, Sanjay Natarajan, Ramune Nagisetty, Sunit Tyagi, Guiseppe Curello
  • Publication number: 20060145273
    Abstract: Embodiments of the invention provide a transistor with stepped source and drain regions. The stepped regions may provide significant strain in a channel region while minimizing current leakage. The stepped regions may be formed by forming two recesses in a substrate to result in a stepped recess, and forming the source/drain regions in the recesses.
    Type: Application
    Filed: January 6, 2005
    Publication date: July 6, 2006
    Inventors: Giuseppe Curello, Bernhard Sell, Sunit Tyagi, Chris Auth
  • Publication number: 20060084216
    Abstract: Various methods for forming a layer of strained silicon in a channel region of a device and devices constructed according to the disclosed methods. In one embodiment, a strain-inducing layer is formed, a relaxed layer is formed on the strain-inducing layer, a portion of the strain-inducing layer is removed, which allows the strain-inducing layer to relax and strain the relaxed layer.
    Type: Application
    Filed: December 1, 2005
    Publication date: April 20, 2006
    Inventors: Stephen Cea, Ravindra Soman, Ramune Nagisetty, Sunit Tyagi, Sanjay Natarajan
  • Publication number: 20060065937
    Abstract: A method of providing a halo implant region in a substrate of a MOS device having a gate electrode thereon and defining source/drain regions, a MOS device fabricated according to the above method, and a system comprising the MOS device. The method comprises: defining undercut recesses in the substrate at the source/drain regions thereof, the undercut recesses extending beneath the gate electrode; creating a halo implant region beneath the gate electrode between the recesses; and providing raised source/drain structures in the undercut recesses after creating the halo implant region.
    Type: Application
    Filed: September 30, 2004
    Publication date: March 30, 2006
    Inventors: Thomas Hoffmann, Sunit Tyagi, Giuseppe Curello, Berhard Sell, Christopher Auth
  • Patent number: 7019326
    Abstract: Various methods for forming a layer of strained silicon in a channel region of a device and devices constructed according to the disclosed methods. In one embodiment, a strain-inducing layer is formed, a relaxed layer is formed on the strain-inducing layer, a portion of the strain-inducing layer is removed, which allows the strain-inducing layer to relax and strain the relaxed layer.
    Type: Grant
    Filed: November 14, 2003
    Date of Patent: March 28, 2006
    Assignee: Intel Corporation
    Inventors: Stephen M. Cea, Ravindra Soman, Ramune Nagisetty, Sunit Tyagi, Sanjay Natarajan
  • Publication number: 20050106792
    Abstract: Various methods for forming a layer of strained silicon in a channel region of a device and devices constructed according to the disclosed methods. In one embodiment, a strain-inducing layer is formed, a relaxed layer is formed on the strain-inducing layer, a portion of the strain-inducing layer is removed, which allows the strain-inducing layer to relax and strain the relaxed layer.
    Type: Application
    Filed: November 14, 2003
    Publication date: May 19, 2005
    Inventors: Stephen Cea, Ravindra Soman, Ramune Nagisetty, Sunit Tyagi, Sanjay Natarajan
  • Patent number: 6787440
    Abstract: A method for making a semiconductor device is described. That method comprises forming on a substrate a buffer layer and a high-k gate dielectric layer, oxidizing the surface of the high-k gate dielectric layer, and then forming a gate electrode on the oxidized high-k gate dielectric layer.
    Type: Grant
    Filed: December 10, 2002
    Date of Patent: September 7, 2004
    Assignee: Intel Corporation
    Inventors: Christopher G. Parker, Markus Kuhn, Ying Zhou, Scott A. Hareland, Suman Datta, Nick Lindert, Robert S. Chau, Timothy E. Glassman, Matthew V. Metz, Sunit Tyagi
  • Publication number: 20040110361
    Abstract: A method for making a semiconductor device is described. That method comprises forming on a substrate a buffer layer and a high-k gate dielectric layer, oxidizing the surface of the high-k gate dielectric layer, and then forming a gate electrode on the oxidized high-k gate dielectric layer.
    Type: Application
    Filed: December 10, 2002
    Publication date: June 10, 2004
    Inventors: Christopher G. Parker, Markus Kuhn, Ying Zhou, Scott A. Hareland, Suman Datta, Nick Lindert, Robert S. Chau, Timothy E. Glassman, Matthew V. Metz, Sunit Tyagi
  • Publication number: 20040080356
    Abstract: A pair of C-shaped gate electrodes may define a pair of transistors and a pair of diodes for forming an input/output signal driver for electrostatic discharge protection. Because of the compact arrangement, silicon real estate may be conserved in silicon-on-insulator substrates.
    Type: Application
    Filed: October 25, 2002
    Publication date: April 29, 2004
    Inventors: Scott A. Hareland, Sunit Tyagi
  • Patent number: 6458667
    Abstract: An improved MOS transistor and method for making it are described. The MOS transistor's source and drain have a first conductivity type and are separated from each other by a first region having a second conductivity type opposite to the first conductivity type. A second region, also having the second conductivity type, is formed adjacent to the drain and is separated from the first region by the drain.
    Type: Grant
    Filed: March 21, 2000
    Date of Patent: October 1, 2002
    Assignee: Intel Corporation
    Inventors: Sunit Tyagi, Shahriar S. Ahmed
  • Publication number: 20020063292
    Abstract: Complementary metal oxide semiconductor transistors are formed on a silicon substrate. The substrate has a {100} crystallographic orientation. The transistors are formed on the substrate so that current flows in the channels of the transistors are parallel to the <100>direction. Additionally, longitudinal tensile stress is applied to the channels.
    Type: Application
    Filed: November 29, 2000
    Publication date: May 30, 2002
    Inventors: Mark Armstrong, Gerhard Schrom, Sunit Tyagi, Paul A. Packan, Kelin J. Kuhn, Scott Thompson
  • Patent number: 6384457
    Abstract: Metal Oxide Semiconductor Field Effect Transistors (MOSFET) are disclosed. One MOSFET includes, a substrate having a well of a first conductivity type. The MOSFET also includes source and drain regions, of a second conductivity type, formed in the well arranged apart from each other. Moreover, the MOSFET includes a first region, of a second conductivity type, formed in the well near the drain region. The first region has a low doping. Furthermore, the MOSFET includes a second region of a second conductivity type, formed near the source region. The second region has a doping substantially higher than the doping of the first region. A second MOSFET includes a substrate having a well of a first conductivity type and source and drain regions, of a second conductivity type, formed in the well apart from each other. Moreover, the MOSFET includes a drain extension region of the second conductivity type, formed in the well near the drain region.
    Type: Grant
    Filed: May 3, 1999
    Date of Patent: May 7, 2002
    Assignee: Intel Corporation
    Inventors: Sunit Tyagi, Shahriar S. Ahmed
  • Patent number: 6372583
    Abstract: A method for making a semiconductor device. In that method, source and drain regions are epitaxially grown on a first part of a substrate. After a gate oxide is formed on a second part of the substrate, an etched polysilicon layer is formed on the gate oxide.
    Type: Grant
    Filed: February 9, 2000
    Date of Patent: April 16, 2002
    Assignee: Intel Corporation
    Inventor: Sunit Tyagi
  • Patent number: 6297104
    Abstract: Metal Oxide Semiconductor Field Effect Transistors (MOSFET) are disclosed. One MOSFET includes, a substrate having a well of a first conductivity type. The MOSFET also includes source and drain regions, of a second conductivity type, formed in the well arranged apart from each other. Moreover, the MOSFET includes a first region, of a second conductivity type, formed in the well near the drain region. The first region has a low doping. Furthermore, the MOSFET includes a second region of a second conductivity type, formed near the source region. The second region has a doping substantially higher than the doping of the first region. A second MOSFET includes a substrate having a well of a first conductivity type and source and drain regions, of a second conductivity type, formed in the well apart from each other. Moreover, the MOSFET includes a drain extension region of the second conductivity type, formed in the well near the drain region.
    Type: Grant
    Filed: February 2, 2000
    Date of Patent: October 2, 2001
    Assignee: Intel Corporation
    Inventors: Sunit Tyagi, Shahriar S. Ahmed
  • Publication number: 20010013628
    Abstract: Metal Oxide Semiconductor Field Effect Transistors (MOSFET) are disclosed. One MOSFET includes, a substrate having a well of a first conductivity type. The MOSFET also includes source and drain regions, of a second conductivity type, formed in the well arranged apart from each other. Moreover, the MOSFET includes a first region, of a second conductivity type, formed in the well near the drain region. The first region has a low doping. Furthermore, the MOSFET includes a second region of a second conductivity type, formed near the source region. The second region has a doping substantially higher than the doping of the first region. A second MOSFET includes a substrate having a well of a first conductivity type and source and drain regions, of a second conductivity type, formed in the well apart from each other. Moreover, the MOSFET includes a drain extension region of the second conductivity type, formed in the well near the drain region.
    Type: Application
    Filed: May 3, 1999
    Publication date: August 16, 2001
    Inventors: SUNIT TYAGI, SHAHRIAR S. AHMED
  • Patent number: 6249025
    Abstract: The present invention is a semiconductor device having and a method for forming wells by growing an epitaxial silicon layer wherein the epitaxial silicon layer has at least three silicon sublayers. The first sublayer is highly doped, the second sublayer is less doped, and the third sublayer is also highly doped. The use of the epitaxially grown wells allows for the placement of high dopant concentrations in regions of the well where electrical isolation is an issue and the placement of lower doped concentrations in regions of the well where electrical isolation is not as great an issue in order to help reduce the problem of parasitic capacitance.
    Type: Grant
    Filed: December 29, 1997
    Date of Patent: June 19, 2001
    Assignee: Intel Corporation
    Inventor: Sunit Tyagi
  • Patent number: 6200879
    Abstract: The present invention is a semiconductor device having and a method for forming wells by growing an epitaxial silicon layer wherein the epitaxial silicon layer has at least three silicon sublayers. The first sublayer is highly doped, the second sublayer is less doped, and the third sublayer is also highly doped. The use of the epitaxially grown wells allows for the placement of high dopant concentrations in regions of the well where electrical isolation is an issue and the placement of lower doped concentrations in regions of the well where electrical isolation is not as great an issue in order to help reduce the problem of parasitic capacitance.
    Type: Grant
    Filed: December 10, 1998
    Date of Patent: March 13, 2001
    Assignee: Intel Corporation
    Inventor: Sunit Tyagi
  • Patent number: 6177705
    Abstract: An improved MOS transistor and method for making it are described. The MOS transistor's source and drain have a first conductivity type and are separated from each other by a first region having a second conductivity type opposite to the first conductivity type. A second region, also having the second conductivity type, is formed adjacent to the drain and is separated from the first region by the drain.
    Type: Grant
    Filed: August 12, 1999
    Date of Patent: January 23, 2001
    Assignee: Intel Corporation
    Inventors: Sunit Tyagi, Shahriar S. Ahmed