Patents by Inventor Sunit Tyagi

Sunit Tyagi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6297104
    Abstract: Metal Oxide Semiconductor Field Effect Transistors (MOSFET) are disclosed. One MOSFET includes, a substrate having a well of a first conductivity type. The MOSFET also includes source and drain regions, of a second conductivity type, formed in the well arranged apart from each other. Moreover, the MOSFET includes a first region, of a second conductivity type, formed in the well near the drain region. The first region has a low doping. Furthermore, the MOSFET includes a second region of a second conductivity type, formed near the source region. The second region has a doping substantially higher than the doping of the first region. A second MOSFET includes a substrate having a well of a first conductivity type and source and drain regions, of a second conductivity type, formed in the well apart from each other. Moreover, the MOSFET includes a drain extension region of the second conductivity type, formed in the well near the drain region.
    Type: Grant
    Filed: February 2, 2000
    Date of Patent: October 2, 2001
    Assignee: Intel Corporation
    Inventors: Sunit Tyagi, Shahriar S. Ahmed
  • Publication number: 20010013628
    Abstract: Metal Oxide Semiconductor Field Effect Transistors (MOSFET) are disclosed. One MOSFET includes, a substrate having a well of a first conductivity type. The MOSFET also includes source and drain regions, of a second conductivity type, formed in the well arranged apart from each other. Moreover, the MOSFET includes a first region, of a second conductivity type, formed in the well near the drain region. The first region has a low doping. Furthermore, the MOSFET includes a second region of a second conductivity type, formed near the source region. The second region has a doping substantially higher than the doping of the first region. A second MOSFET includes a substrate having a well of a first conductivity type and source and drain regions, of a second conductivity type, formed in the well apart from each other. Moreover, the MOSFET includes a drain extension region of the second conductivity type, formed in the well near the drain region.
    Type: Application
    Filed: May 3, 1999
    Publication date: August 16, 2001
    Inventors: SUNIT TYAGI, SHAHRIAR S. AHMED
  • Patent number: 6249025
    Abstract: The present invention is a semiconductor device having and a method for forming wells by growing an epitaxial silicon layer wherein the epitaxial silicon layer has at least three silicon sublayers. The first sublayer is highly doped, the second sublayer is less doped, and the third sublayer is also highly doped. The use of the epitaxially grown wells allows for the placement of high dopant concentrations in regions of the well where electrical isolation is an issue and the placement of lower doped concentrations in regions of the well where electrical isolation is not as great an issue in order to help reduce the problem of parasitic capacitance.
    Type: Grant
    Filed: December 29, 1997
    Date of Patent: June 19, 2001
    Assignee: Intel Corporation
    Inventor: Sunit Tyagi
  • Patent number: 6200879
    Abstract: The present invention is a semiconductor device having and a method for forming wells by growing an epitaxial silicon layer wherein the epitaxial silicon layer has at least three silicon sublayers. The first sublayer is highly doped, the second sublayer is less doped, and the third sublayer is also highly doped. The use of the epitaxially grown wells allows for the placement of high dopant concentrations in regions of the well where electrical isolation is an issue and the placement of lower doped concentrations in regions of the well where electrical isolation is not as great an issue in order to help reduce the problem of parasitic capacitance.
    Type: Grant
    Filed: December 10, 1998
    Date of Patent: March 13, 2001
    Assignee: Intel Corporation
    Inventor: Sunit Tyagi
  • Patent number: 6177705
    Abstract: An improved MOS transistor and method for making it are described. The MOS transistor's source and drain have a first conductivity type and are separated from each other by a first region having a second conductivity type opposite to the first conductivity type. A second region, also having the second conductivity type, is formed adjacent to the drain and is separated from the first region by the drain.
    Type: Grant
    Filed: August 12, 1999
    Date of Patent: January 23, 2001
    Assignee: Intel Corporation
    Inventors: Sunit Tyagi, Shahriar S. Ahmed
  • Patent number: 5844300
    Abstract: A monitoring device to monitor process induced charge employing a single layer of polysilicon forming a floating gate. The device comprises two capacitors, one for charging and the other for discharging a floating gate of an n-channel transistor. Embodiments which permit the monitoring of positive charge, negative charge and both positive and negative charge are described. The device is reusable and lends itself to in-line monitoring as opposed to some prior art devices used for end-of-line monitoring.
    Type: Grant
    Filed: September 19, 1996
    Date of Patent: December 1, 1998
    Assignee: Intel Corporation
    Inventors: Mohsen Alavi, Payman Aminzadeh, Robert A. Gasser, Sunit Tyagi, Gilroy J. Vandentop