Abstract: A display panel and a method for driving the display panel, and a display apparatus. The display panel comprises a pixel circuit, the pixel circuit includes a driving module, a gate reset module electrically connected between a first signal line and a control node, a threshold compensation module electrically connected between an output end of the driving module and the control node, and a control module electrically connected between the control node and a control terminal of the driving module. A driving cycle of the pixel circuit comprises an initialization period, a charging period, and a light-emitting control period. The gate reset module is turned on during the initialization period, the threshold compensation module is turned on at least during the charging period, and the control module is turned on during the initialization period and the charging period and is turned off during the light-emitting control period.

Abstract: A display panel includes a substrate and driver circuits disposed on one side of the substrate. A driver circuit includes at least two transistors. Gates of two transistors are connected to different control signal terminals. The display panel further includes shielding structures disposed on one side of the substrate facing the driver circuit. The shielding structures include shielding sub-structures each of which at least partially overlaps a channel region of one of the two preceding transistors. Different shielding sub-structures are connected to different potential signal terminals.

Abstract: A display panel, driving method for the same and display apparatus. An input terminal and output terminals of a demultiplexer are coupled to a data terminal and at least two data lines, respectively; one transistor is connected to one corresponding data line, the data line connected to a first transistor and the data line connected to a second transistor is coupled to a plurality of first sub-pixels and a plurality of second and/or third sub-pixels, respectively; a control terminal of the first transistor is coupled to a first control line, and a control terminal of the second transistor is coupled to a second control line; the first control line includes a first wiring section, which is greater than the second control line in line width; and/or the first wiring section includes a first and second sub-wiring arranged in different layers and connected with each other by at least two vias.

Abstract: Provided in the embodiments of the present discourse are a display panel, a driving method for the same, and a display device. The display panel includes: a first shift register including a plurality of cascaded first shift units; a first signal line electrically connected to the plurality of first shift units for providing a level voltage required to be output by the first shift units; and a second signal line receiving a same level voltage as the first signal line, where at least one switch unit is connected between the second signal line and the first signal line. The display panel has a first mode, and in the first mode, the first shift units output at least two pluses within one frame, and at least a part of the switch units are turned on.

Abstract: A shift register, a driver circuit, a display panel, and a display apparatus. In the shift register, a first input unit is configured to write a signal into a first node; a first output unit includes a control terminal coupled to the first node, a first terminal receiving a first voltage signal, and a second terminal coupled to a signal output terminal; a second input unit is configured to write a signal into a second node; a second output unit includes a control terminal coupled to the second node, a first terminal receiving a first clock signal, and a second terminal coupled to the signal output terminal; a holding unit includes an output terminal coupled to the second node, and is configured to maintain a potential of the second node at least during a period when the first output unit is off and the second output unit is on.

Abstract: A shift register, a method for driving a shift register, a gate driving circuit and a display panel are provided. The shift register includes: a first output device, where a control terminal thereof is electrically connected to a first node, a first terminal thereof is electrically connected to a first clock signal terminal, and a second terminal thereof is electrically connected to an output terminal of the shift register; a first node control device including a first switch device and a second switch device, where the first switch device is electrically connected to the first node, a first power supply voltage signal terminal and a second node, and the second switch device is electrically connected to the second node, the first power supply voltage signal terminal and the first node.

Abstract: A liquid crystal display (LCD) panel and an LCD device are provided. The LCD panel includes a display area, a gate driver on array (GOA) circuit area, and a first common electrode line disposed therebetween. A plurality of virtual pixels are disposed on a side of the display area near the GOA circuit area and are arranged along a column direction. Each of the virtual pixels includes a virtual pixel electrode, and the first common electrode line is connected to each of the virtual pixel electrodes.

Abstract: The present disclosure provides a liquid crystal display panel and a display device. The liquid crystal display panel includes an array substrate. A hollow structure is defined in a common electrode layer. The hollow structure includes a first hollow structure corresponding to a display area. An area of the first hollow structure progressively increases along a direction from an array routing area to the display area, so that an area of the common electrode layer corresponding to the display area progressively decreases along the direction from the array routing area to the display area, thereby making RC loadings uniform and keeping charging rates in various areas same.

Abstract: The present application discloses a shift register and a method for driving the shift register, a light-emission control circuit and a display panel. The shift register includes an input module, a control module, a pull-up module, an output module and a maintenance module. The input module is connected to an input end, a first clock end, a first level end, a first node and a second node. The control module is connected to the first node, a third node, and a second clock end. The pull-up module is connected to the second node, a second level end, and the third node. The output module is connected to the second node, the third node, the first level end, and the second level end. The maintenance module is connected to the second node, the first level end and the second level end.

Abstract: The present application discloses a shift register and a method for driving the shift register, a light-emission control circuit and a display panel. The shift register includes an input module, a control module, a pull-up module, an output module and a maintenance module. The input module is connected to an input end, a first clock end, a first level end, a first node and a second node. The control module is connected to the first node, a third node, and a second clock end. The pull-up module is connected to the second node, a second level end, and the third node. The output module is connected to the second node, the third node, the first level end, and the second level end. The maintenance module is connected to the second node, the first level end and the second level end.

Abstract: A shift register, a method for driving a shift register, a gate driving circuit and a display panel are provided. The shift register includes: a first output device, where a control terminal thereof is electrically connected to a first node, a first terminal thereof is electrically connected to a first clock signal terminal, and a second terminal thereof is electrically connected to an output terminal of the shift register; a first node control device including a first switch device and a second switch device, where the first switch device is electrically connected to the first node, a first power supply voltage signal terminal and a second node, and the second switch device is electrically connected to the second node, the first power supply voltage signal terminal and the first node.

Abstract: A pixel layout and a display panel having the pixel layout are provided. The pixel layout includes a plurality of pixel repeating groups, and each of the pixel repeating groups is formed by two adjacent pixels. Two through-holes are positioned between the two pixels, and first ends of the two through-holes are respectively connected to pixel electrodes of the pixels. When one of the pixel electrodes of the two pixels has a voltage loss and the pixel thereof presents a dark spot, second ends of the two through-holes are connected to allow the pixel having the dark spot to display normally with help of the other pixel, thereby repairing the dark spot.

Abstract: A gate driver on array (GOA) circuit and a display panel are provided. The GOA circuit includes a plurality of cascaded GOA units. The GOA units include a first GOA unit and a second GOA unit. By setting a virtual reset module in the second GOA unit, and the virtual reset module corresponding to the reset module in the first GOA unit, a difference between the first GOA unit and the second GOA unit is reduced and stability of the GOA circuit is improved.

Abstract: A liquid crystal display (LCD) panel and an LCD device are provided. The LCD panel includes a display area, a gate driver on array (GOA) circuit area, and a first common electrode line disposed therebetween. A plurality of virtual pixels are disposed on a side of the display area near the GOA circuit area and are arranged along a column direction. Each of the virtual pixels includes a virtual pixel electrode, and the first common electrode line is connected to each of the virtual pixel electrodes.

Abstract: A gate driving circuit and a display panel are provided. The gate driving circuit reduces the number of transistors through the inverter in the pull-down maintaining circuit such that the number of the signal output ends connected to the inverter is reduced. In this way, the number of the other transistors in the pull-down maintaining circuit is also reduced. Therefore, the number of the transistors and the number of the signal output ends of the pull-down maintaining circuit are both reduced. This means that the number of the transistors and the number of the signal output ends of the gate driving circuit are both reduced.

Abstract: The present disclosure provides a liquid crystal display panel and a display device. The liquid crystal display panel includes an array substrate. A hollow structure is defined in a common electrode layer. The hollow structure includes a first hollow structure corresponding to a display area. An area of the first hollow structure progressively increases along a direction from an array routing area to the display area, so that an area of the common electrode layer corresponding to the display area progressively decreases along the direction from the array routing area to the display area, thereby making RC loadings uniform and keeping charging rates in various areas same.

Abstract: A gate driver on array (GOA) circuit and a display panel are provided. The GOA circuit includes a plurality of cascaded GOA units. The GOA units include a first GOA unit and a second GOA unit. By setting a virtual reset module in the second GOA unit, and the virtual reset module corresponding to the reset module in the first GOA unit, a difference between the first GOA unit and the second GOA unit is reduced and stability of the GOA circuit is improved.

Abstract: A gate driver on array (GOA) circuit and a display panel including the same are provided. The GOA circuit includes: a GOA drive signal line including a voltage common (VCOM) signal line, a start vertical (STV) signal line, a reference voltage (VSS) signal line, and a low-frequency clock (LC) signal line; and a GOA protection circuit, wherein an end of the GOA protection circuit is connected to the VCOM signal line, and another end thereof is electrically connected to the STV signal line, the VSS signal line, and the LC signal line.

Abstract: A gate driving circuit and a display panel are provided. The gate driving circuit reduces the number of transistors through the inverter in the pull-down maintaining circuit such that the number of the signal output ends connected to the inverter is reduced. In this way, the number of the other transistors in the pull-down maintaining circuit is also reduced. Therefore, the number of the transistors and the number of the signal output ends of the pull-down maintaining circuit are both reduced. This means that the number of the transistors and the number of the signal output ends of the gate driving circuit are both reduced.

Abstract: The present invention provides an array substrate and a manufacturing method thereof, an array substrate includes a sub-pixel including a main-region and a sub-region. A gate line is disposed between the main-region and the sub-region, and two adjacent data lines define a pixel boundary. A transparent common electrode line is respectively disposed corresponding to the main-region and the sub-region. Wherein, a projection range of the pixel electrode on the substrate covers a projection range of part of the transparent common electrode line corresponding to a direction of the data line on the substrate.