Abstract: An array substrate, a method of manufacturing thereof, and a display panel are provided. In the array substrate, a lesser thickness of an active layer in a GOA area achieves improved response time of thin film transistor in the GOA area, and a greater thickness of the active layer in a display area reduces diffusion of photons in the active layer, so as to decrease an influence of negative bias of thin film transistor in the display area. Additionally, different demands for characteristics of the array substrate in the display area and in the GOA area may be met, such that quality of the display panel may be improved.

Abstract: A GOA circuit and a display panel are provided. In the GOA circuit, a first clock signal, a second clock signal, and a nth stage clock signal are separated into an input terminal of a first unit and an input terminal of a second unit. This reduces time that a thin film transistor in an inverter is subjected to forward current stress, thereby reducing offset of a threshold voltage of the thin film transistor, improving stability of the thin film transistor, and ensuring a normal output of a scan signal waveform.

Abstract: A control circuit and a display panel applied by the control circuit are provided. The control circuit includes a plurality of stages of shift registers, wherein each of the shift registers includes a first switch, wherein a control terminal of the first switch is configured to receive a first control signal, a first terminal of the first switch is configured to receive the first control signal, and a second terminal of the first switch is electrically coupled to a first node; a second switch, wherein a control terminal of the second switch is electrically coupled to the first node, a first terminal of the second switch is configured to receive a first clock signal, and a second terminal of the second switch is configured to receive a second control signal.

Abstract: A control circuit and a display panel applied by the control circuit are provided. The control circuit includes a plurality of stages of shift registers, wherein each of the shift registers includes a first switch, wherein a control terminal of the first switch is configured to receive a first control signal, a first terminal of the first switch is configured to receive the first control signal, and a second terminal of the first switch is electrically coupled to a first node; a second switch, wherein a control terminal of the second switch is electrically coupled to the first node, a first terminal of the second switch is configured to receive a first clock signal, and a second terminal of the second switch is configured to receive a second control signal.

Abstract: A gate on array (GOA) circuit and a display panel are provided. The GOA circuit includes a plurality of GOA units connected in series. A pull-up module includes a first switch, a second switch, a third switch and a fourth switch. When a nth stage signal STn corresponds to a high voltage level, the third switch is turned on and residual charges of the first switch, the second switch and the third switch are released through an output end of the fourth switch to prevent the residual charges from influencing performances of the first switch, the second switch, the third switch and the fourth switch.

Abstract: The present invention provides an array substrate and a manufacturing method thereof, an array substrate includes a sub-pixel including a main-region and a sub-region. A gate line is disposed between the main-region and the sub-region, and two adjacent data lines define a pixel boundary. A transparent common electrodes line is respectively disposed corresponding to the main-region and the sub-region. Wherein, a projection range of the pixel electrode on the substrate covers a projection range of part of the transparent common electrode line corresponding to a direction of the data line on the substrate.

Abstract: Disclosed is a bootstrap capacitor of a gate driver on array (GOA) circuit, comprising: a first branch capacitor; and a second branch capacitor, located above the first branch capacitor, wherein the second branch capacitor is connected in parallel with the first branch capacitor, and a projection of the second branch capacitor at least partially overlaps a projection of the first branch capacitor in a horizontal plane to reduce a width of the bootstrap capacitor. Further disclosed are a GOA circuit and a display panel. There is an advantage of reducing a width occupied by a bootstrap capacitor.