Abstract: A gate on array (GOA) device and a gate driving circuit are provided. The GOA device includes at least two GOA units. Each of the at least two GOA units includes at least one pull-down maintenance unit. The pull-down maintenance unit at least includes a first thin film transistor. The first thin film transistor includes a base substrate, a first electrode, a second electrode, and a third electrode. An electric potential of the first electrode is different from an electric potential of the second electrode. The first electrode or the second electrode is electrically connected to the third electrode.

Abstract: A gate on array (GOA) device and a gate driving circuit are provided. The GOA device includes at least two GOA units. Each of the at least two GOA units includes at least one pull-down maintenance unit. The pull-down maintenance unit at least includes a first thin film transistor. The first thin film transistor includes a base substrate, a first electrode, a second electrode, and a third electrode. An electric potential of the first electrode is different from an electric potential of the second electrode. The first electrode or the second electrode is electrically connected to the third electrode.

Abstract: A gate driver on array (GOA) circuit and a display panel are provided. The GOA circuit includes a plurality of cascaded GOA units. Switching transistor devices are added to an inverter of the GOA unit, and a low-potential signal is output to relevant nodes in the inverter in time to release residual charge of the relevant nodes.

Abstract: A gate driver on array (GOA) circuit and a display panel are provided. A pull-down maintaining module of the GOA circuit includes an eleventh transistor and a twelfth transistor to remove a residual charge of a second node and a third node to enhance a stability of the GOA circuit.

Abstract: An array substrate and a display panel are provided. The present disclosure can form a capacitor by having a first metal layer which forms a start pulse signal line to be a first plate, and having a second metal layer which is connected to a peripheral common electrode line to be a second plate, thereby achieving electrostatic protection. In addition, by designing the start pulse signal line from an original wire-wound type to a grid shape, accumulated electric charges accumulated in the start pulse signal line can be effectively eliminated, thereby reducing probability of electrostatic discharge in the start pulse signal line.

Abstract: An array substrate and a display panel are provided. The present disclosure can form a capacitor by having a first metal layer which forms a start pulse signal line to be a first plate, and having a second metal layer which is connected to a peripheral common electrode line to be a second plate, thereby achieving electrostatic protection. In addition, by designing the start pulse signal line from an original wire-wound type to a grid shape, accumulated electric charges accumulated in the start pulse signal line can be effectively eliminated, thereby reducing probability of electrostatic discharge in the start pulse signal line.

Abstract: An inverter, a gate driver on array circuit, and a display panel are provided. The inverter includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first test transistor, a second test transistor, and a third test transistor. A gate and a source of the first transistor and a source of the third transistor are electrically connected to a first test signal line, a drain of the first transistor, a drain of the second transistor is electrically connected to a first node, a gate of the second transistor and a gate of the fourth transistor are electrically connected to the pull-up node, and a drain of the third transistor and a drain of the fourth transistor are electrically connected to a second node.

Abstract: An array substrate, a method of manufacturing thereof, and a display panel are provided. In the array substrate, a lesser thickness of an active layer in a GOA area achieves improved response time of thin film transistor in the GOA area, and a greater thickness of the active layer in a display area reduces diffusion of photons in the active layer, so as to decrease an influence of negative bias of thin film transistor in the display area. Additionally, different demands for characteristics of the array substrate in the display area and in the GOA area may be met, such that quality of the display panel may be improved.

Abstract: The array substrate comprises: a substrate including a first region, a second region, and a third region; a first metal layer is disposed on the substrate and forms a gate metal and a common line; a first insulating layer is disposed on the substrate and the first metal layer; a second metal layer is disposed on the first insulating layer and forms a source/drain metal; a second insulating layer is disposed on the first insulating layer and the second metal layer; and a third metal layer is disposed on the second insulating layer and forms a voltage signal line.

Abstract: The present application provides an array substrate and a display panel. The array substrate comprises: a substrate; a first metal layer; a first insulating layer; a second metal layer disposed on the first insulating layer, the second metal layer forming a scan line, a first connection metal, and a first drain of the first thin film transistor; a second insulating layer; a third metal layer disposed on the second insulating layer, the third metal layer being electrically connected to the first gate, and a portion of the third metal layer opposite to the first connecting metal forms a bootstrap capacitor.

Abstract: A gate driver on array (GOA) circuit and a display panel are provided. The GOA circuit includes a plurality of cascaded GOA units. Switching transistor devices are added to an inverter of the GOA unit, and a low-potential signal is output to relevant nodes in the inverter in time to release residual charge of the relevant nodes.

Abstract: A gate driver on array (GOA) circuit and a display panel are provided. A pull-down maintaining module of the GOA circuit includes an eleventh transistor and a twelfth transistor to remove a residual charge of a second node and a third node to enhance a stability of the GOA circuit.

Abstract: The array substrate comprises: a substrate including a first region, a second region, and a third region; a first metal layer is disposed on the substrate and forms a gate metal and a common line; a first insulating layer is disposed on the substrate and the first metal layer; a second metal layer is disposed on the first insulating layer and forms a source/drain metal; a second insulating layer is disposed on the first insulating layer and the second metal layer; and a third metal layer is disposed on the second insulating layer and forms a voltage signal line.

Abstract: A gate driver on array (GOA) circuit and a display panel including the same are provided. The GOA circuit includes: a GOA drive signal line including a voltage common (VCOM) signal line, a start vertical (STV) signal line, a reference voltage (VSS) signal line, and a low-frequency clock (LC) signal line; and a GOA protection circuit, wherein an end of the GOA protection circuit is connected to the VCOM signal line, and another end thereof is electrically connected to the STV signal line, the VSS signal line, and the LC signal line.

Abstract: A pixel layout and a display panel having the pixel layout are provided. The pixel layout includes a plurality of pixel repeating groups, and each of the pixel repeating groups is formed by two adjacent pixels. Two through-holes are positioned between the two pixels, and first ends of the two through-holes are respectively connected to pixel electrodes of the pixels. When one of the pixel electrodes of the two pixels has a voltage loss and the pixel thereof presents a dark spot, second ends of the two through-holes are connected to allow the pixel having the dark spot to display normally with help of the other pixel, thereby repairing the dark spot.

Abstract: A transistor structure, a gate on array (GOA) circuit, and a display panel are provided. The transistor structure includes a substrate, and a source/drain electrode layer and a passivation layer which are disposed on the substrate sequentially. Furthermore, the source/drain electrode layer includes a source electrode and a drain electrode, and the source electrode is arranged around the drain electrode and is in an annular shape. The passivation layer includes a via hole. A projection of the drain electrode on the passivation layer covers the via hole.

Abstract: The present disclosure provides a gate driver on array (GOA) circuit and a liquid crystal display panel. A blocking unit is disposed in each stages of GOA units. When a first node is at a high voltage potential and a stage signal is also at a high voltage potential, a first control signal and a second control signal are at a low voltage potential and both gates of a twelfth thin-film transistor (TFT) and a thirteenth TFT are at the low voltage potential so that gate-source voltage differences between the twelfth TFT and the thirteenth TFT are large enough to properly turn off the twelfth TFT and the thirteenth TFT. Thus, current leakage of the first node is prevented.

Abstract: An inverter, a gate driver on array circuit, and a display panel are provided. The inverter includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first test transistor, a second test transistor, and a third test transistor. A gate and a source of the first transistor and a source of the third transistor are electrically connected to a first test signal line, a drain of the first transistor, a drain of the second transistor is electrically connected to a first node, a gate of the second transistor and a gate of the fourth transistor are electrically connected to the pull-up node, and a drain of the third transistor and a drain of the fourth transistor are electrically connected to a second node.

Abstract: The present disclosure provides a gate driver on array (GOA) circuit and a liquid crystal display panel. A blocking unit is disposed in each stages of GOA units. When a first node is at a high voltage potential and a stage signal is also at a high voltage potential, a first control signal and a second control signal are at a low voltage potential and both gates of a twelfth thin-film transistor (TFT) and a thirteenth TFT are at the low voltage potential so that gate-source voltage differences between the twelfth TFT and the thirteenth TFT are large enough to properly turn off the twelfth TFT and the thirteenth TFT. Thus, current leakage of the first node is prevented.

Abstract: A GOA circuit and a display panel are provided. In the GOA circuit, a first clock signal, a second clock signal, and a nth stage clock signal are separated into an input terminal of a first unit and an input terminal of a second unit. This reduces time that a thin film transistor in an inverter is subjected to forward current stress, thereby reducing offset of a threshold voltage of the thin film transistor, improving stability of the thin film transistor, and ensuring a normal output of a scan signal waveform.