Abstract: A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming a dielectric stack atop the semiconductor substrate comprising an insulating interlayer atop a high k dielectric; removing the insulating interlayer from the nFET region without removing the insulating interlayer from the pFET region; and providing at least one gate stack in the pFET region and at least one gate stack in the nFET region. The insulating interlayer can be AlN or AlOxNy. The high k dielectric can be HfO2, hafnium silicate or hafnium silicon oxynitride. The insulating interlayer can be removed from the nFET region by a wet etch including a HCl/H2O2 peroxide solution.

Abstract: A MOSFET is disclosed that comprises a channel between a source extension and a drain extension, a dielectric layer over the channel, a gate spacer structure formed on a peripheral portion of the dielectric layer, and a gate formed on a non-peripheral portion of the dielectric layer, with at least a lower portion of the gate surrounded by and in contact with an internal surface of the gate spacer structure, and the gate is substantially aligned at its bottom with the channel. One method of forming the MOSFET comprises forming the dielectric layer, the gate spacer structure and the gate contact inside a cavity that has been formed by removing a sacrificial gate and spacer structure.

Abstract: Techniques for combining nanotechnology with photovoltaics are provided. In one aspect, a method of forming a photovoltaic device is provided comprising the following steps. A plurality of nanowires are formed on a substrate, wherein the plurality of nanowires attached to the substrate comprises a nanowire forest. In the presence of a first doping agent and a first volatile precursor, a first doped semiconductor layer is conformally deposited over the nanowire forest. In the presence of a second doping agent and a second volatile precursor, a second doped semiconductor layer is conformally deposited over the first doped layer. The first doping agent comprises one of an n-type doping agent and a p-type doping agent and the second doping agent comprises a different one of the n-type doping agent and the p-type doping agent from the first doping agent. A transparent electrode layer is deposited over the second doped semiconductor layer.

Abstract: A heater includes at least two leads, and a heating element which is formed between the at least two leads, a material of the heating element being different from a material of the at least two leads such that a location of a hot spot in the heater is controllable based on a polarity of current in the heater.

Abstract: A method (and resultant structure) of forming a semiconductor structure, includes forming a mixed rare earth oxide on silicon. The mixed rare earth oxide is lattice-matched to silicon.

Abstract: A method of placing a functionalized semiconducting nanostructure, includes functionalizing a semiconducting nanostructure including one of a nanowire and a nanocrystal, with an organic functionality including a functional group for bonding to a bonding surface, dispersing the functionalized semiconducting nanostructure in a solvent to form a dispersion, and depositing the dispersion onto the bonding surface.

Abstract: A method (and resultant structure) of forming a semiconductor structure, includes forming a mixed rare earth oxide on silicon. The mixed rare earth oxide is lattice-matched to silicon.

Abstract: In one embodiment, the invention is a method and apparatus for flatband voltage tuning of high-k field effect transistors. One embodiment of a field effect transistor includes a substrate, a high-k dielectric layer deposited on the substrate, a gate electrode deposited on the high-k dielectric layer, and a dipole layer positioned between the substrate and the gate electrode, for shifting the threshold voltage of the field effect transistor.

Abstract: In one embodiment, the invention is a method and apparatus for flatband voltage tuning of high-k field effect transistors. One embodiment of a field effect transistor includes a substrate, a high-k dielectric layer deposited on the substrate, a gate electrode deposited on the high-k dielectric layer, and a dipole layer positioned between the substrate and the gate electrode, for shifting the threshold voltage of the field effect transistor.

Abstract: A method of forming an electropositive metal-containing capping layer atop a stack of a high k gate dielectric/interfacial layer that avoids chemically and physically altering the high k gate dielectric and the interfacial layer is provided. The method includes chemical vapor deposition of an electropositive metal-containing precursor at a temperature that is about 400° C. or less. The present invention also provides semiconductor structures such as, for example, MOSCAPs and MOSFETs, that include a chemical vapor deposited electropositive metal-containing capping layer atop a stack of a high k gate dielectric and an interfacial layer. The presence of the CVD electropositive metal-containing capping layer does not physically or chemically alter the high k gate dielectric and the interfacial layer.

Abstract: Photovoltaic devices and techniques for enhancing efficiency thereof are provided. In one aspect, a photovoltaic device is provided. The photovoltaic device comprises a photocell having a photoactive layer and a non-photoactive layer adjacent to the photoactive layer so as to form a heterojunction between the photoactive layer and the non-photoactive layer; and a plurality of high-aspect-ratio nanostructures on one or more surfaces of the photoactive layer. The plurality of high-aspect-ratio nanostructures are configured to act as a scattering media for incident light. The plurality of high-aspect-ratio nanostructures can also be configured to create an optical resonance effect in the incident light.

Abstract: Photovoltaic devices and techniques for enhancing efficiency thereof are provided. In one aspect, a photovoltaic device is provided. The photovoltaic device comprises a photocell having a first photoactive layer and a second photoactive layer adjacent to the first photoactive layer so as to form a heterojunction between the first photoactive layer and the second photoactive layer; and a plurality of high-aspect-ratio nanostructures on one or more surfaces of the second photoactive layer. The plurality of high-aspect-ratio nanostructures are configured to act as a scattering media for incident light. The plurality of high-aspect-ratio nanostructures can also be configured to create an optical resonance effect in the incident light.

Abstract: The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first gate stack of pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride.

Abstract: A MOSFET is disclosed that comprises a channel between a source extension and a drain extension, a dielectric layer over the channel, a gate spacer structure formed on a peripheral portion of the dielectric layer, and a gate formed on a non-peripheral portion of the dielectric layer, with at least a lower portion of the gate surrounded by and in contact with an internal surface of the gate spacer structure, and the gate is substantially aligned at its bottom with the channel. One method of forming the MOSFET comprises forming the dielectric layer, the gate spacer structure and the gate contact inside a cavity that has been formed by removing a sacrificial gate and spacer structure.

Abstract: Solar concentrator devices and techniques for the fabrication thereof are provided. In one aspect, a solar concentrator device is provided. The solar concentrator device comprises at least one solar converter cell; a heat sink; and a liquid metal between the solar converter cell and the heat sink, configured to thermally couple the solar converter cell and the heat sink during operation of the device. The solar converter cell can comprise a triple-junction semiconductor solar converter cell fabricated on a germanium (Ge) substrate. The heat sink can comprise a vapor chamber heat sink. The liquid metal can comprise a gallium (Ga) alloy and have a thermal resistance of less than or equal to about five square millimeter degree Celsius per Watt (mm2° C./W).

Abstract: A structure (e.g., field effect transistor) and a method for making the structure, include a substrate having a source region, a drain region, and a channel region therebetween, an insulating layer disposed over the channel region, the insulating layer including a layer including aluminum nitride disposed over the channel region, and a gate electrode disposed over the insulating layer.

Abstract: The present invention provides a method for removing charged defects from a material stack including a high k gate dielectric and a metal contact such that the final gate stack, which is useful in forming a pFET device, has a threshold voltage substantially within the silicon band gap and good carrier mobility. Specifically, the present invention provides a re-oxidation procedure that will restore the high k dielectric of a pFET device to its initial, low-defect state. It was unexpectedly determined that by exposing a material stack including a high k gate dielectric and a metal to dilute oxygen at low temperatures will substantially eliminate oxygen vacancies, resorting the device threshold to its proper value. Furthermore, it was determined that if dilute oxygen is used, it is possible to avoid undue oxidation of the underlying semiconductor substrate which would have a deleterious effect on the capacitance of the final metal-containing gate stack.

Abstract: The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first stack of a pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride.

Abstract: A MOSFET is disclosed that comprises a channel between a source extension and a drain extension, a dielectric layer over the channel, a gate spacer structure formed on a peripheral portion of the dielectric layer, and a gate formed on a non-peripheral portion of the dielectric layer, with at least a lower portion of the gate surrounded by and in contact with an internal surface of the gate spacer structure, and the gate is substantially aligned at its bottom with the channel.

Abstract: A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming a dielectric stack atop the semiconductor substrate comprising an insulating interlayer atop a high k dielectric; removing the insulating interlayer from the nFET region without removing the insulating interlayer from the pFET region; and providing at least one gate stack in the pFET region and at least one gate stack in the nFET region. The insulating interlayer can be AlN or AlOxNy. The high k dielectric can be HfO2, hafnium silicate or hafnium silicon oxynitride. The insulating interlayer can be removed from the nFET region by a wet etch including a HCl/H2O2 peroxide solution.