Patents by Inventor Suraj J. Mathew
Suraj J. Mathew has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150001605Abstract: A method of forming a gate construction of a recessed access device includes forming a pair of sidewall spacers laterally over opposing sidewalls of a gate dielectric and elevationally over first conductive gate material. The gate dielectric, the first conductive gate material, and the sidewall spacers are received within a trench formed in semiconductive material. Second conductive gate material is deposited within the semiconductive material trench between the pair of sidewall spacers in electrical connection with the first conductive gate material. Other implementations are disclosed, including recessed access device gate constructions independent of method of manufacture.Type: ApplicationFiled: September 16, 2014Publication date: January 1, 2015Inventors: Suraj J. Mathew, Jaydip Guha
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Publication number: 20140315364Abstract: Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed.Type: ApplicationFiled: June 30, 2014Publication date: October 23, 2014Inventors: Jaydip Guha, Shyam Surthi, Suraj J. Mathew, Kamal M. Karda, Hung-Ming Tsai
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Patent number: 8790977Abstract: Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed.Type: GrantFiled: November 14, 2013Date of Patent: July 29, 2014Assignee: Micron Technology, Inc.Inventors: Jaydip Guha, Shyam Surthi, Suraj J. Mathew, Kamal M. Karda, Hung-Ming Tsai
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Patent number: 8754443Abstract: Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided allow trace wiring in a memory array to be formed on or near a surface of a memory device.Type: GrantFiled: September 15, 2012Date of Patent: June 17, 2014Assignee: Micron Technology, Inc.Inventors: Suraj J. Mathew, Chandra Mouli
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Patent number: 8722480Abstract: Transistors are provided including first and second source/drain regions, a channel region and a gate stack having a first gate dielectric over a substrate, the first gate dielectric having a dielectric constant higher than a dielectric constant of silicon dioxide, and a metal material in contact with the first gate dielectric, the metal material being doped with an inert element. Integrated circuits including the transistors and methods of forming the transistors are also provided.Type: GrantFiled: January 28, 2013Date of Patent: May 13, 2014Assignee: Micron Technology, Inc.Inventors: F. Daniel Gealy, Suraj J. Mathew, Cancheepuram V. Srividya
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Publication number: 20140073100Abstract: Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed.Type: ApplicationFiled: November 14, 2013Publication date: March 13, 2014Applicant: Micron Technology, Inc.Inventors: Jaydip Guha, Shyam Surthi, Suraj J. Mathew, Kamal M. Karda, Hung-Ming Tsai
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Patent number: 8609488Abstract: Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed.Type: GrantFiled: April 24, 2013Date of Patent: December 17, 2013Assignee: Micron Technology, Inc.Inventors: Jaydip Guha, Shyam Surthi, Suraj J. Mathew, Kamal M. Karda, Hung-Ming Tsai
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Publication number: 20130237023Abstract: Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed.Type: ApplicationFiled: April 24, 2013Publication date: September 12, 2013Applicant: Micron Technology, Inc.Inventors: Jaydip Guha, Shyam Surthi, Suraj J. Mathew, Kamal M. Karda, Hung-Ming Tsai
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Patent number: 8455919Abstract: Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided allow trace wiring in a memory array to be formed on or near a surface of a memory device.Type: GrantFiled: July 19, 2010Date of Patent: June 4, 2013Assignee: Micron Technology, Inc.Inventors: Suraj J. Mathew, Chandra Mouli
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Patent number: 8450175Abstract: Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed.Type: GrantFiled: February 22, 2011Date of Patent: May 28, 2013Assignee: Micron Technology, Inc.Inventors: Jaydip Guha, Shyam Surthi, Suraj J. Mathew, Kamal M. Karda, Hung-Ming Tsai
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Publication number: 20130087840Abstract: A memory cell includes a transistor device comprising a pair of source/drains, a body comprising a channel, and a gate construction operatively proximate the channel. The memory cell includes a capacitor comprising a pair of capacitor electrodes having a capacitor dielectric there-between. One of the capacitor electrodes is the channel or is electrically coupled to the channel. The other of the capacitor electrodes includes a portion of the body other than the channel. Methods are also disclosed.Type: ApplicationFiled: October 7, 2011Publication date: April 11, 2013Inventors: Kamal M. Karda, Suraj J. Mathew, Jaydip Guha
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Publication number: 20130009208Abstract: Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided allow trace wiring in a memory array to be formed on or near a surface of a memory device.Type: ApplicationFiled: September 15, 2012Publication date: January 10, 2013Inventors: Suraj J Mathew, Chandra Mouli
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Publication number: 20120214285Abstract: Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed.Type: ApplicationFiled: February 22, 2011Publication date: August 23, 2012Inventors: Jaydip Guha, Shyam Surthi, Suraj J. Mathew, Kamal M. Karda, Hung-Ming Tsai
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Publication number: 20120012892Abstract: Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided allow trace wiring in a memory array to be formed on or near a surface of a memory device.Type: ApplicationFiled: July 19, 2010Publication date: January 19, 2012Inventors: Suraj J. Mathew, Chandra Mouli
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Patent number: 8067286Abstract: The invention includes methods of forming recessed access devices. A substrate is provided to have recessed access device trenches therein. A pair of the recessed access device trenches are adjacent one another. Electrically conductive material is formed within the recessed access device trenches, and source/drain regions are formed proximate the electrically conductive material. The electrically conductive material and source/drain regions together are incorporated into a pair of adjacent recessed access devices. After the recessed access device trenches are formed within the substrate, an isolation region trench is formed between the adjacent recessed access devices and filled with electrically insulative material to form a trenched isolation region.Type: GrantFiled: January 24, 2011Date of Patent: November 29, 2011Assignee: Micron Technology, Inc.Inventors: Kunal R. Parekh, Suraj J. Mathew, Jigish D. Trivedi, John K. Zahurak, Sanh D. Tang
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Patent number: 7005342Abstract: An improved method of making CMOS surface channel transistors using fewer masking steps. In-situ doped poly silicon deposition can be used to reduce problems with poly depletion effects in transistor gates. In addition, using this method, the number of layers in each gate dielectric, the dielectric type, and dielectric thickness between n-channel and p-channel devices can be separately controlled. This method also allows the use of a lithography mask normally used to fabricate buried channel devices for use in fabricating surface channel devices, thus saving the manufacture of an additional mask.Type: GrantFiled: August 30, 2004Date of Patent: February 28, 2006Assignee: Micron Technology, Inc.Inventors: Suraj J. Mathew, Jigish D. Trivedi
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Patent number: 6809014Abstract: An improved method of making CMOS surface channel transistors using fewer masking steps. In-situ doped poly silicon deposition can be used to reduce problems with poly depletion effects in transistor gates. In addition, using this method, the number of layers in each gate dielectric, the dielectric type, and dielectric thickness between n-channel and p-channel devices can be separately controlled. This method also allows the use of a lithography mask normally used to fabricate buried channel devices for use in fabricating surface channel devices, thus saving the manufacture of an additional mask.Type: GrantFiled: March 14, 2001Date of Patent: October 26, 2004Assignee: Micron Technology, Inc.Inventors: Suraj J. Mathew, Jigish D. Trivedi
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Patent number: 6797596Abstract: A method used during the formation of a semiconductor device reduces ion channeling during implantation of the wafer. The method comprises providing a semiconductor wafer and an unetched transistor gate stack assembly over the wafer. The unetched transistor gate stack assembly comprises a gate oxide layer, a control gate layer, a metal layer, and a dielectric capping layer. A patterned photoresist layer is formed over the unetched transistor gate stack assembly, then each of the capping layer, the metal layer, the control gate layer, and the gate oxide layer is etched to form a plurality of laterally-spaced transistor gate stacks. A screening layer is formed overlying the semiconductor wafer between the transistor gate stacks. A dopant is implanted into the semiconductor wafer through the screening layer, then the screening layer is removed.Type: GrantFiled: August 29, 2002Date of Patent: September 28, 2004Assignee: Micron Technology, Inc.Inventors: Fawad Ahmed, Jigish D. Trivedi, Suraj J Mathew
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Publication number: 20040043586Abstract: A method used during the formation of a semiconductor device reduces ion channeling during implantation of the wafer. The method comprises providing a semiconductor wafer and an unetched transistor gate stack assembly over the wafer. The unetched transistor gate stack assembly comprises a gate oxide layer, a control gate layer, a metal layer, and a dielectric capping layer. A patterned photoresist layer is formed over the unetched transistor gate stack assembly, then each of the capping layer, the metal layer, the control gate layer, and the gate oxide layer is etched to form a plurality of laterally-spaced transistor gate stacks. A screening layer is formed overlying the semiconductor wafer between the transistor gate stacks. A dopant is implanted into the semiconductor wafer through the screening layer, then the screening layer is removed.Type: ApplicationFiled: August 29, 2002Publication date: March 4, 2004Inventors: Fawad Ahmed, Jigish D. Trivedi, Suraj J. Mathew
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Publication number: 20020132412Abstract: An improved method of making CMOS surface channel transistors using fewer masking steps. In-situ doped poly silicon deposition can be used to reduce problems with poly depletion effects in transistor gates. In addition, using this method, the number of layers in each gate dielectric, the dielectric type, and dielectric thickness between n-channel and p-channel devices can be separately controlled. This method also allows the use of a lithography mask normally used to fabricate buried channel devices for use in fabricating surface channel devices, thus saving the manufacture of an additional mask.Type: ApplicationFiled: March 14, 2001Publication date: September 19, 2002Applicant: Micron Technology, Inc.Inventors: Suraj J. Mathew, Jigish D. Trivedi