Gate Constructions Of Recessed Access Devices And Methods Of Forming Gate Constructions Of Recessed Access Devices
A method of forming a gate construction of a recessed access device includes forming a pair of sidewall spacers laterally over opposing sidewalls of a gate dielectric and elevationally over first conductive gate material. The gate dielectric, the first conductive gate material, and the sidewall spacers are received within a trench formed in semiconductive material. Second conductive gate material is deposited within the semiconductive material trench between the pair of sidewall spacers in electrical connection with the first conductive gate material. Other implementations are disclosed, including recessed access device gate constructions independent of method of manufacture.
This patent resulted from a divisional application of U.S. patent application Ser. No. 12/833,071, filed Jul. 9, 2010, entitled “Gate Constructions Of Recessed Access Devices And Methods Of Forming Gate Constructions Of Recessed Access Devices”, naming Suraj J. Mathew and Jaydip Guha as inventors, the disclosure of which is incorporated by reference.
TECHNICAL FIELDEmbodiments disclosed herein pertain to gate constructions of recessed access devices and to methods of forming gate constructions of recessed access devices.
BACKGROUNDEmbodiments of the invention were motivated in addressing current leakage that occurs in recessed access devices. A recessed access device is a field effect transistor having its gate construction received within a trench formed in semiconductive material. The gate construction includes a gate dielectric which lines the trench and conductive gate material received within the trench laterally inward of the gate dielectric. Source/drain regions are formed within the semiconductive material on opposing sides of the trench in outermost regions of the semiconductive material. Application of suitable voltage to the conductive gate material within the trench enables current to flow through the semiconductive material between the source/drains along the trench sidewalls and around the base of the trench.
Gate induced drain leakage (GIDL) is a negative attribute associated with field effect transistors, and can be problematic with recessed access devices, particularly at the elevationally outermost regions of the source/drains adjacent the uppermost portions of the trench.
Embodiments of the invention encompass methods of forming a gate construction of a recessed access device. The discussion initially proceeds with reference to
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First conductive gate material 32 has been deposited over gate dielectric 26 within semiconductive material trenches 24 in memory array area 12 and over gate dielectric 26 in peripheral circuitry area 14. Material 32 may be deposited to physically contact gate dielectric 26. Material 32 may be homogenous or non-homogenous, and may comprise any one or combination of elemental metals, alloys of elemental metals, conductive metal compounds, and/or conductively doped semiconductive material. Conductively doped polysilicon is one example. An example thickness for first conductive gate material 32 is about half of an ultimate desired thickness of the conductive portions of gate constructions in the peripheral circuitry area where gate constructions are to be there-fabricated. An example thickness range is from about 250 Angstroms to about 450 Angstroms, with about 350 Angstroms being a specific example. In one embodiment, an etch barrier 34 may be deposited over first conductive gate material 32 in memory array area 12 and in peripheral circuitry area 14. An example material is silicon nitride deposited to an example thickness of about 300 Angstroms. Such may be used to protect the outermost surface of first conductive gate material 32 within peripheral circuitry area 14 during processing specific to memory array area 12. In one embodiment, a photoresist-comprising material 36 may be formed over etch barrier 34. Such may be homogenous or non-homogenous comprising multiple different composition materials and/or layers.
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Processing may proceed subsequently in fabrication of completed field effect transistor devices using recessed access gate constructions 50 within memory array area 12 and gate constructions 52 within peripheral circuitry area 14. For example as shown in
Example alternate embodiments of a method of forming recessed access device gate constructions within a memory array area and peripheral circuitry gate constructions in a peripheral circuitry area are next described with reference to
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In one embodiment of the invention, a method of forming a gate construction of a recessed access device includes forming a pair of sidewall spacers laterally over opposing sidewalls of a gate dielectric and above first conductive gate material. The gate dielectric, the first conductive gate material, and the spacers over which such are formed are collectively received within a trench formed in semiconductive material. Such spacers may or may not project outwardly of the semiconductive material in which the trench is formed. Further, other material may or may not be received over the semiconductive material in which the trench is formed. The above-described embodiments show spacers 42 and 42a as projecting elevationally outward of a trench 24 in semiconductive material 16. Alternately and by way of example, such spacers might have uppermost surfaces which are elevationally coincident with uppermost surfaces 17 of material 16 immediately adjacent a trench 24, or which are recessed within a trench 24 below such surfaces 17. However, greater reduction in GIDL may occur by having dielectric spacers 42/42a project elevationally outward of material 16 as shown.
Regardless, second conductive gate material is deposited within the semiconductive material trench between the pair of sidewall spacers to be in electrical connection with the first conductive gate material. One or more attributes may be as described above with respect to composition, deposition, and any subsequent patterning with respect to the first and second conductive gate materials.
In one embodiment of the invention, a method of forming a gate construction of a recessed access device comprises forming gate dielectric and first conductive gate material within a trench in semiconductive material. The first conductive gate material is recessed, for example by etching, within the trench to have an elevationally outermost (upper) surface that spans completely across the trench between the gate dielectric. A pair of etched sidewall spacers is formed within the trench laterally over opposing sidewalls of the gate dielectric and over the first conductive gate material. Second conductive gate material is deposited within the trench between the pair of etched sidewall spacers in electrical connection with the first conductive gate material.
Embodiments of the invention also encompass recessed access device gate constructions independent of method of fabrication. In one embodiment, such a gate construction comprises a trench within semiconductive material, with the trench comprising semiconductive material sidewalls and a semiconductive material base extending between the semiconductive material sidewalls. A gate dielectric lining is received over the semiconductive material trench sidewalls and the semiconductive material trench base. A pair of laterally spaced and laterally opposed blocks is received within an upper portion of the trench, and which project laterally into the trench. The above-described sidewall spacers are example such blocks. Regardless, the blocks are laterally thicker than thickness of the gate dielectric lining that is received over the trench sidewalls and the trench base. Conductive gate material is received within the trench between and below the blocks, and extends elevationally outward of the semiconductive material trench to elevationally over the dielectric blocks.
In one embodiment, the conductive portion of the gate construction is wider in cross section above and below the blocks than there-between. Any one or other attributes of the constructions as described above and/or shown in the drawings may constitute an attribute of such a recessed access device gate construction.
In compliance with the statute, the subject matter disclosed herein has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the claims are not limited to the specific features shown and described, since the means herein disclosed comprise example embodiments. The claims are thus to be afforded full scope as literally worded, and to be appropriately interpreted in accordance with the doctrine of equivalents.
Claims
1-21. (canceled)
22. A method of forming recessed access device gate constructions within a memory array area and peripheral circuitry gate constructions in a peripheral circuitry area, comprising:
- forming peripheral circuitry gate dielectric and conductive peripheral circuitry gate material over a peripheral circuitry area and over a memory array area of a semiconductor substrate;
- in the memory array area, etching recessed access device trenches through the conductive peripheral circuitry gate material and through the peripheral circuitry gate dielectric to within semiconductive material under the peripheral circuitry gate dielectric;
- forming memory array gate dielectric over sidewalls of the semiconductive material within the trenches in the memory array area;
- depositing first conductive gate material over the memory array gate dielectric within the semiconductive material trenches in the memory array area;
- in the memory array area, etching the first conductive gate material to recess it within the trenches to below elevationally outermost surfaces of the semiconductive material adjacent the trenches and exposing memory array gate dielectric within the trenches;
- in the memory array area, forming etched sidewall spacers that are above and below the elevationally outermost surfaces of the semiconductive material adjacent the trenches;
- depositing second conductive gate material within the trenches between the etched spacers and in electrical connection with the first conductive gate material within the memory array area and over and in electrical connection with the conductive peripheral circuitry gate material in the peripheral circuitry area; and
- in a single masking step, removing the second conductive gate material within the memory array area to form recessed access device gate constructions within the memory array area and removing the second conductive gate material and the conductive peripheral circuitry gate material within the peripheral circuitry area to form peripheral circuitry gate constructions.
23. The method of claim 0 comprising forming an oxidation barrier over the conductive peripheral gate material in the memory array area and in the peripheral circuitry area prior to etching the trenches.
24. The method of claim 23 wherein the oxidation barrier comprises Si3N4.
25. The method of claim 23 comprising removing the oxidation barrier after the gate dielectric is formed.
26. The method of claim 25 comprising removing the oxidation barrier before forming the etched sidewall spacers.
27. The method of claim 0 comprising:
- depositing the second conductive gate material elevationally over the etched spacers; and
- patterning the second conductive gate material such that the respective conductive portions of the gate constructions are wider in cross section above and below the etched spacers than there-between.
28. A recessed access device gate construction comprising:
- a trench within semiconductive material, the trench comprising semiconductive material sidewalls and a semiconductive material base extending between the semiconductive material sidewalls;
- a gate dielectric lining over the semiconductive material trench sidewalls and the semiconductive material trench base;
- blocks received within an upper portion of the trench which project laterally into the trench, the blocks being laterally thicker than thickness of the gate dielectric lining received over the trench sidewalls and trench base; and
- conductive gate material received within the trench between, below, and above the blocks.
29. The gate construction of claim 28 wherein the conductive portion of the gate construction is wider in cross section above and below the blocks than there-between.
30. The gate construction of claim 27 wherein the blocks protrude above the semiconductive material in which the trench is received.
31. The gate construction of claim 30 wherein the conductive portion of the gate construction is wider in cross section above and below the blocks than there-between.
32. The gate construction of claim 28 wherein the blocks are wider at their bottoms than at their tops.
33. The gate construction of claim 28 wherein the blocks have lateral sidewall surfaces, the conductive gate material that is over the blocks having lateral sidewall surfaces that are laterally coincident with those of the blocks.
34. The gate construction of claim 33 wherein the blocks protrude above the semiconductive material in which the trench is received.
35. The method of claim 22 wherein the sidewall spacers are formed by anisotropic etching.
36. The method of claim 22 wherein the first and second conductive gate materials are of the same composition.
37. The method of claim 22 wherein the second conductive gate material is deposited into physical contact with the first conductive gate material that is within the trench.
Type: Application
Filed: Sep 16, 2014
Publication Date: Jan 1, 2015
Inventors: Suraj J. Mathew (Boise, ID), Jaydip Guha (Boise, ID)
Application Number: 14/487,201
International Classification: H01L 29/423 (20060101); H01L 21/28 (20060101);