Abstract: A data consistency analyzer identifies data inconsistencies proactively, providing insights into the financial, business, and technical impact to enable users to make decisions regarding resolution of the inconsistencies. The data consistency analyzer may provide additional insights such as criticality of inconsistencies. Data inconsistencies may be caused by configuration changes to master data. As described herein, data consistency is improved by keeping a constant watch on various master data changes which is one of the major sources towards causing inconsistency and taking necessary actions based on further assessments. Using master data change as initial lead, the inconsistencies would be identified that are not mere database or technical inconsistencies. Along with the primary option of inconsistency check based on master data change, additional options to scan the system based on overall run and run per selection, or application level specific checks will be provided.

Abstract: A provider institution computing system includes a customer database storing customer information, a network interface circuit structured to enable an exchange of information over a network, and a transaction circuit generating trackable transaction requests.

Abstract: Methods, systems, and devices for a read operation using compressed memory are described. An apparatus may include a host system coupled with a non-volatile memory device and a volatile memory device. The host system may store, in the volatile memory device, a compressed copy of data stored in the non-volatile memory device, for example, based on a score assigned to the data. The host system may identify that the compressed copy of the data is stored in the volatile memory device and may transmit a read command to the volatile memory device that includes a logical address associated with a logical block address of the data stored in the non-volatile memory device. The host system may receive the compressed copy of the data from the volatile memory device in response to the read command and may decompress the data.

Abstract: According to one example embodiment, a computer implemented method performed by a funds transfer computing system, includes registering a beneficiary to a rating system. Registering the beneficiary comprises receiving identifying information including at least one of a receiving account, a financial institution associated with the receiving account, a beneficiary location, a beneficiary name, and an authentication factor. An identity of the beneficiary is validated in response to the received identifying information. A trust score for the beneficiary is generated. The trust score is indicative of the beneficiary's likelihood of being approved to receive funds in an international funds transfer between the beneficiary and a payor.

Abstract: Technology is described herein for searching an index, including operations of: obtaining a source data item; generating a source context-supplemented vector based on the source data item; and searching the index to find one or more target context-supplemented vectors that are determined to match the source context-supplemented vector. Each context-supplemented vector, which is associated with a particular data item, is made up of two parts: a language-agnostic vector and a context vector. The language-agnostic vector expresses the meaning of the particular data item in a manner that is independent of a natural language that is used to express the particular data item, while the context vector expresses a context associated with the formation of the particular data item. More generally, the technology's use of context vectors allows it to perform index search operations in a more efficient manner, compared to a search engine that does not use context vectors.

Abstract: A data consistency analyzer identifies data inconsistencies proactively, providing insights into the financial, business, and technical impact to enable users to make decisions regarding resolution of the inconsistencies. The data consistency analyzer may provide additional insights such as criticality of inconsistencies. Data inconsistencies may be caused by configuration changes to master data. As described herein, data consistency is improved by keeping a constant watch on various master data changes which is one of the major sources towards causing inconsistency and taking necessary actions based on further assessments. Using master data change as initial lead, the inconsistencies would be identified that are not mere database or technical inconsistencies. Along with the primary option of inconsistency check based on master data change, additional options to scan the system based on overall run and run per selection, or application level specific checks will be provided.

Abstract: The present disclosure provides a method of treating a subject having a cancer. The method comprises reducing expression of a Carm 1 gene and/or a Carm 1 effector gene in a cell of the subject, and/or reducing activity of a Carm 1 protein and/or a Carm 1 effector protein in a cell of the subject. The cancer is resistant to immunotherapy and/or checkpoint blockade treatment.

Abstract: Methods, systems, and devices for power supply control for non-volatile memory are described. A package containing a memory subsystem may include a controller, a volatile memory, and a non-volatile memory. The package may include one or more pins for receiving a supply voltage that may be distributed to the controller, the volatile memory, and the non-volatile memory using one or more power supply rails. The memory subsystem may include one or more switching components along one or more power supply rails to selectively decouple the non-volatile memory from the one or more power supply rails, thereby enabling the non-volatile memory to be powered down separately from the controller and volatile memory. The controller may determine whether to couple or uncouple the non-volatile memory from a power supply rail based on various criteria associated with accessing the non-volatile memory.

Abstract: Methods, systems, and devices for dynamic logical page sizes for memory devices are described. A memory device may use an initial set of logical pages each having a same size and one or more logical-to-physical (L2P) tables to map logical addresses of the logical pages to the physical addresses of corresponding physical pages. As commands are received from a host device, the memory device may dynamically split a logical page to introduce smaller logic pages if the host device accesses data in chunk sizes smaller than the size of the logical page that is split. The memory device may maintain one or more additional L2P tables for each smaller logical page size that is introduced, along with one or more pointer tables to map between L2P tables and entries for larger logical page sizes and L2P tables and entries associated with smaller logical page sizes.

Abstract: A low dropout regulator includes a proportional-to-absolute-temperature (PTAT) circuit, an amplification circuit, and an output circuit. The PTAT circuit outputs one current, and the amplification circuit outputs one or more currents. The one or more currents are outputted by the amplification circuit based on collector-emitter voltages associated with transistors of the PTAT circuit. Alternatively, the one or more currents are outputted by the amplification circuit based on the current outputted by the PTAT circuit and the collector-emitter voltages associated with the transistors of the PTAT circuit. The output circuit generates one or more output voltages based on at least one of a base-emitter voltage associated with a transistor of the PTAT circuit and a current of the one or more currents outputted by the amplification circuit.

Abstract: Embodiments include an interface processing system for displaying interrelated hierarchical building system models. The interface processing system can include memory and a processor allocation to load an executable asset from a data store to instantiate an instance of a building management service that can receive from a client application executing an operator interface on a client device, a request to display a visual representation of an asset located in a building. The service can query an asset database including structured data associated with the asset. Location data can be used to generate a digital model of a building system location associated with the asset. The building management service can retrieve structured model data for the asset and system level components and extract, from a set of asset schemas, a hierarchical relationship between the asset, locations and the system level components to generate an interactive visual representation of the building system location.

Abstract: Methods, systems, and devices for write buffer extensions for storage interface controllers are described. Apparatuses and methods are presented in which a buffer may be used to temporarily store data from an application if the memory device is in an INACTIVE power mode. This may allow the memory device to remain asleep. The buffer may be positioned on the host device so that the power mode of the memory device may not affect it. That way, data may be stored in the buffer without waking up the memory device. If the memory device is in an ACTIVE power mode, the data that has been temporarily stored in the buffer may be sent to the memory device for storage. During read operations, if the requested data is stored in the buffer, it may be used instead of data in the memory device.

Abstract: Technology is described herein for searching an index, including operations of: obtaining a source data item; generating a source context-supplemented vector based on the source data item; and searching the index to find one or more target context-supplemented vectors that are determined to match the source context-supplemented vector. Each context-supplemented vector, which is associated with a particular data item, is made up of two parts: a language-agnostic vector and a context vector. The language-agnostic vector expresses the meaning of the particular data item in a manner that is independent of a natural language that is used to express the particular data item, while the context vector expresses a context associated with the formation of the particular data item. More generally, the technology’s use of context vectors allows it to perform index search operations in a more efficient manner, compared to a search engine that does not use context vectors.

Abstract: Methods, systems, and devices for session-based memory operation are described. A memory system may determine that a logical address targeted by a read command is associated with a session table. The memory system may write the session table to a cache based on the logical address being associated with the session table. After writing the session table to the cache, the memory system may use the session table to determine one or more logical-to-physical (L2P) tables and write the one or more L2P tables to the cache. The memory system may use the L2L tables to perform address translation for logical addresses.

Abstract: Methods, systems, and devices for rate adjustments for a memory interface are described. A host system may communicate with a memory system via an interface according to multiple data transfer rates. For example, the host system may configure the interface to operate according to a first rate. The host system may switch the interface from the first rate to a second rate in response to one or more commands from the host system satisfying one or more parameters such as a threshold quantity of data associated with a command, a threshold quantity of issued commands associated with at least the threshold quantity of data, a threshold quantity of issued and unexecuted commands, or any combination thereof. Based on the switching, the host system may communicate with the memory system via the interface in accordance with the second rate.

Abstract: Aspects of the present disclosure are directed to devices and methods for performing MAC operations using a memory array as a compute-in-memory (CIM) device that can enable higher computational throughput, higher performance and lower energy consumption compared to computation using a processor outside of a memory array. In some embodiments, an activation architecture is provided using a bit cell array arranged in rows and columns to store charges that represent a weight value in a weight matrix. A read word line (RWL) may be repurposed to provide the input activation value to bit cells within a row of bit cells, while a read-bit line (RBL) is configured to receive multiplication products from bit cells arranged in a column. Some embodiments provide multiple sub-arrays or tiles of bit cell arrays.

Abstract: Systems and methods for generating an application store metadata corresponding to a plurality of sub-applications, combining model-driven application and canvas-type applications. Lifecycle components of the plurality of sub-applications are coupled to each other using one or more data relationships defined by an embedding model and the stored metadata. The metadata points to a library associated with the plurality of sub-applications, and wherein the library comprises a newest version of one or more of the lifecycle components. The compiled plurality of sub-applications can then be run.

Abstract: A low dropout regulator includes a proportional-to-absolute-temperature (PTAT) circuit, an amplification circuit, and an output circuit. The PTAT circuit outputs one current, and the amplification circuit outputs one or more currents. The one or more currents are outputted by the amplification circuit based on collector-emitter voltages associated with transistors of the PTAT circuit. Alternatively, the one or more currents are outputted by the amplification circuit based on the current outputted by the PTAT circuit and the collector-emitter voltages associated with the transistors of the PTAT circuit. The output circuit generates one or more output voltages based on at least one of a base-emitter voltage associated with a transistor of the PTAT circuit and a current of the one or more currents outputted by the amplification circuit.

Abstract: Methods, systems, and devices for dynamic logical page sizes for memory devices are described. A memory device may use an initial set of logical pages each having a same size and one or more logical-to-physical (L2P) tables to map logical addresses of the logical pages to the physical addresses of corresponding physical pages. As commands are received from a host device, the memory device may dynamically split a logical page to introduce smaller logic pages if the host device accesses data in chunk sizes smaller than the size of the logical page that is split. The memory device may maintain one or more additional L2P tables for each smaller logical page size that is introduced, along with one or more pointer tables to map between L2P tables and entries for larger logical page sizes and L2P tables and entries associated with smaller logical page sizes.

Abstract: Systems and methods relating to generating trackable transaction requests are disclosed. A financial institution computing system includes a customer database storing financial information and tracking information, a network interface circuit enabling the financial institution computing system to exchange information over a network, and a transaction circuit generating trackable transaction requests across a plurality of financial institutions. The transaction circuit receives financial information from an originator computing system over the network and generates a corresponding transaction request including a transaction identification code. The transaction request is transmitted to a correspondent institution over the network and tracking information is received from at least one correspondent institution. The tracking information is provided to the originator computing system the transaction circuit settles the transaction request.