Abstract: Methods, systems, and devices for dynamic logical page sizes for memory devices are described. A memory device may use an initial set of logical pages each having a same size and one or more logical-to-physical (L2P) tables to map logical addresses of the logical pages to the physical addresses of corresponding physical pages. As commands are received from a host device, the memory device may dynamically split a logical page to introduce smaller logic pages if the host device accesses data in chunk sizes smaller than the size of the logical page that is split. The memory device may maintain one or more additional L2P tables for each smaller logical page size that is introduced, along with one or more pointer tables to map between L2P tables and entries for larger logical page sizes and L2P tables and entries associated with smaller logical page sizes.

Abstract: Systems and methods relating to generating trackable transaction requests are disclosed. A financial institution computing system includes a customer database storing financial information and tracking information, a network interface circuit enabling the financial institution computing system to exchange information over a network, and a transaction circuit generating trackable transaction requests across a plurality of financial institutions. The transaction circuit receives financial information from an originator computing system over the network and generates a corresponding transaction request including a transaction identification code. The transaction request is transmitted to a correspondent institution over the network and tracking information is received from at least one correspondent institution. The tracking information is provided to the originator computing system the transaction circuit settles the transaction request.

Abstract: An electronic system comprising a voltage-to-current converter and a proportional-to-absolute-temperature (PTAT) circuit is disclosed. The voltage-to-current converter is configured to receive one of a control voltage, a supply voltage, a scaled-down version of the control voltage, and a scaled-down version of the supply voltage, and generate a set of currents. The PTAT circuit is coupled with the voltage-to-current converter such that each current of the set of currents is one of sourced to the PTAT circuit and sank from the PTAT circuit. Further, the PTAT circuit is configured to receive at least one of the supply voltage and the control voltage, and generate a set of reference voltages. The control voltage is generated based on the set of reference voltages and the supply voltage.

Abstract: A plasmonic laser array device may comprise a first microcavity element having a first radiating end facet and a second radiating end facet opposite the first radiating end facet in a longitudinal direction of the device. The device may comprise a second microcavity element having a third radiating end facet and a fourth radiating end facet opposite the third radiating facet in the longitudinal direction. The device may comprise a first microcavity gap configured to separate the first microcavity element and the second microcavity element in the longitudinal direction. The device may comprise a bottom (e.g., metal) layer configured to underly the first microcavity element, the second microcavity element, and the first microcavity gap. The device may comprise an arrangement that places the first microcavity element and the second microcavity element into a phase-locked orientation for a phased-locked operation of the plasmonic laser array device.

Abstract: A bandgap reference voltage generator can include a bandgap core circuit configured to output at least one control voltage. The bandgap reference voltage generator can further include feedback circuitry that can be configured to receive a control voltage outputted by the bandgap core circuit or another control voltage generated based on the control voltage, and output a current. The current can be outputted such that the current is sourced to or sank from the bandgap core circuit. The feedback circuitry can be further configured to generate a bandgap reference voltage. When the current is sourced to the bandgap core circuit, the bandgap reference voltage can be greater than a threshold value. Similarly, when the current is sank from the bandgap core circuit, the bandgap reference voltage can be less than the threshold value.

Abstract: According to a general aspect, an insertion device includes an elongate member defining a lumen, a handle member movably coupled to the elongate member, a plunger member, at least a portion of the plunger member being disposed within the lumen defined by the elongate member, and an actuation member operatively coupled to the plunger member, the plunger member being configured to move from a first position within the lumen to a second location within the lumen in response to the actuation member being actuated.

Abstract: An integrated circuit (IC) includes a self-biased circuit and a start-up circuit for the self-biased circuit. The self-biased circuit generates a start-up indicator signal and an output signal. The start-up indicator signal indicates whether the self-biased circuit has started up. The start-up circuit includes a comparator, a start-up controller, and a peak controller. The comparator compares the start-up indicator signal with a reference signal generated based on supply voltages, and generates a comparison signal. The start-up controller controls a start-up of the self-biased circuit when the comparison signal is at a first logic state. Further, when the comparison signal transitions from the first logic state to a second logic state, the peak controller controls the output signal to maintain one of a voltage level and a current level of the output signal below a peak limit.

Abstract: A bandgap reference voltage generator can include a bandgap core circuit configured to output at least one control voltage. The bandgap reference voltage generator can further include feedback circuitry that can be configured to receive a control voltage outputted by the bandgap core circuit or another control voltage generated based on the control voltage, and output a current. The current can be outputted such that the current is sourced to or sank from the bandgap core circuit. The feedback circuitry can be further configured to generate a bandgap reference voltage. When the current is sourced to the bandgap core circuit, the bandgap reference voltage can be greater than a threshold value. Similarly, when the current is sank from the bandgap core circuit, the bandgap reference voltage can be less than the threshold value.

Abstract: A content addressable memory (CAM) device includes multiple CAM sub-banks Each CAM sub-bank includes an array of CAM cells arranged in rows and columns and partitioned into a first stage and a second stage along a column dimension. Each CAM sub-bank further includes first-stage match lines (MLs), first-stage search line (SL) pairs, second-stage MLs, and second-stage SL pairs. Each second-stage SL pair is coupled to a column of CAM cells in the second stage and is gated by an SL enable (SL_EN signal). Each CAM sub-bank further includes a circuit operative to receive all of the first-stage MLs as input and de-assert the SL_EN signal when none of the first-stage MLs indicate a match. De-assertion of the SL_EN signal blocks a second portion search key from being provided to the second-stage SL pairs.

Abstract: Methods, systems, and devices for a read operation using compressed memory are described. An apparatus may include a host system coupled with a non-volatile memory device and a volatile memory device. The host system may store, in the volatile memory device, a compressed copy of data stored in the non-volatile memory device, for example, based on a score assigned to the data. The host system may identify that the compressed copy of the data is stored in the volatile memory device and may transmit a read command to the volatile memory device that includes a logical address associated with a logical block address of the data stored in the non-volatile memory device. The host system may receive the compressed copy of the data from the volatile memory device in response to the read command and may decompress the data.

Abstract: Methods, systems, and devices for dynamic logical page sizes for memory devices are described. A memory device may use an initial set of logical pages each having a same size and one or more logical-to-physical (L2P) tables to map logical addresses of the logical pages to the physical addresses of corresponding physical pages. As commands are received from a host device, the memory device may dynamically split a logical page to introduce smaller logic pages if the host device accesses data in chunk sizes smaller than the size of the logical page that is split. The memory device may maintain one or more additional L2P tables for each smaller logical page size that is introduced, along with one or more pointer tables to map between L2P tables and entries for larger logical page sizes and L2P tables and entries associated with smaller logical page sizes.

Abstract: Methods, systems, and devices for session-based memory operation are described. A memory system may determine that a logical address targeted by a read command is associated with a session table. The memory system may write the session table to a cache based on the logical address being associated with the session table. After writing the session table to the cache, the memory system may use the session table to determine one or more logical-to-physical (L2P) tables and write the one or more L2P tables to the cache. The memory system may use the L2L tables to perform address translation for logical addresses.

Abstract: An electronic system comprising a voltage-to-current converter and a proportional-to-absolute-temperature (PTAT) circuit is disclosed. The voltage-to-current converter is configured to receive one of a control voltage, a supply voltage, a scaled-down version of the control voltage, and a scaled-down version of the supply voltage, and generate a set of currents. The PTAT circuit is coupled with the voltage-to-current converter such that each current of the set of currents is one of sourced to the PTAT circuit and sank from the PTAT circuit. Further, the PTAT circuit is configured to receive at least one of the supply voltage and the control voltage, and generate a set of reference voltages. The control voltage is generated based on the set of reference voltages and the supply voltage.

Abstract: A technique is directed for managing entitlements within a real-time telemetry system. In an embodiment, access to entitlements is organized between an entitlement management service and an entitlement retrieval service. The entitlement management service may permit users to manage users and roles. The entitlement retrieval service may retrieve logged-in user's entitlements on a restricted basis using the information in an authorization token. The system may maintain separation between the entitlement management application programming interface (API) and entitlement retrieval API within the entitlement service, such that separation between entitlement management APIs, entitlement retrieval APIs, and entitlement enforcements may be enforced.

Abstract: System, apparatus, device, method and/or computer program product are disclosed for making a payment by a customer to a merchant using a peer-to-peer (P2P) payment identification of the customer for a commercial transaction between the merchant and the customer. Embodiments herein provide security protection to the merchant by not revealing a P2P payment identification of the merchant to the customer. A payment request including a customer-facing merchant identification to identify the merchant to the customer is sent to the customer, where the customer-facing merchant identification is different from the P2P payment identification of the merchant. The system is further integrated with a merchant server and the P2P payment system to fulfill the payment to the merchant, to track a status of the payment request, and to determine a status of the commercial transaction between the merchant and the customer.

Abstract: Methods, systems, and devices for power supply control for non-volatile memory are described. A package containing a memory subsystem may include a controller, a volatile memory, and a non-volatile memory. The package may include one or more pins for receiving a supply voltage that may be distributed to the controller, the volatile memory, and the non-volatile memory using one or more power supply rails. The memory subsystem may include one or more switching components along one or more power supply rails to selectively decouple the non-volatile memory from the one or more power supply rails, thereby enabling the non-volatile memory to be powered down separately from the controller and volatile memory. The controller may determine whether to couple or uncouple the non-volatile memory from a power supply rail based on various criteria associated with accessing the non-volatile memory.

Abstract: A switched-capacitor amplifier circuit includes multiple switched-capacitor networks, an amplifier, and multiple reset circuits. The switched-capacitor networks are configured to receive respective input voltages during a sampling phase, and generate sampled voltages. During an amplification phase, the amplifier is coupled with the switched-capacitor networks, and is configured to receive the sampled voltages. The amplifier is further configured to generate output voltages. During the sampling phase, the amplifier is coupled with the reset circuits, and is further configured to receive divided voltages such that the amplifier is reset. The reset circuits are configured to receive and provide a common-mode voltage and the output voltages to the amplifier. The divided voltages are generated based on the common-mode voltage and the output voltages. Each reset circuit includes at least one of a resistor and a capacitor.

Abstract: A switched-capacitor amplifier circuit includes multiple switched-capacitor networks, an amplifier, and multiple reset circuits. The switched-capacitor networks are configured to receive respective input voltages during a sampling phase, and generate sampled voltages. During an amplification phase, the amplifier is coupled with the switched-capacitor networks, and is configured to receive the sampled voltages. The amplifier is further configured to generate output voltages. During the sampling phase, the amplifier is coupled with the reset circuits, and is further configured to receive divided voltages such that the amplifier is reset. The reset circuits are configured to receive and provide a common-mode voltage and the output voltages to the amplifier. The divided voltages are generated based on the common-mode voltage and the output voltages. Each reset circuit includes at least one of a resistor and a capacitor.

Abstract: A pipeline analog-to-digital converter (ADC) includes a hybrid multiplying digital-to-analog converter (MDAC) that includes multiple digital-to-analog converters (DACs), at least one conversion circuit, and at least one amplifier such that a number of conversion circuits and a number of amplifiers is less than a number of DACs. Each DAC is configured to receive an analog input signal in non-overlapping durations of a clock signal and generate a corresponding analog output signal. At least one of the conversion circuits is coupled with at least two DACs, and each conversion circuit is configured to perform conversion operation on a corresponding analog output signal to generate digital signals. At least one of the amplifiers is coupled with at least two DACs, and each amplifier is configured to perform amplification operation on a corresponding analog output signal.

Abstract: A sub-ranging analog-to-digital converter (ADC) includes a coarse ADC and a fine ADC that receives a set of coarse signals from the coarse ADC. The fine ADC includes multiple digital-to-analog converters (DACs) and multiple converters such that a number of converters is less than a number of DACs. The DACs and the converters function in a partial time-interleaved manner where each DAC receives an analog input signal in different non-overlapping durations of a clock signal and generates a corresponding analog output signal. At least one of the converters is coupled with at least two DACs, and each converter is configured to receive the corresponding analog output signals and perform conversion operation to generate digital signals in non-overlapping durations of the clock signal, respectively. The durations for performing conversion operation of at least two of the converters overlap partially.