Abstract: According to one embodiment, an information processing device includes an acquisition part, and a processor. The acquisition part is configured to acquire a reproduction signal obtained from a recording part. The recording part includes a recording medium. The reproduction signal includes a first signal corresponding to information recorded in the recording medium. The processor is configured to derive a first output and a second output. The first output is obtained by first information being processed by a first processing model. The first information includes the first signal. The second output is obtained by the first information being processed by a second processing model. The processor is configured to output a result of processing the first information based on a third output. The third output is obtained based on the first output, the second output, and the first information.

Abstract: According to one embodiment, an information processing device includes an acquisition part, and a processor. The acquisition part is configured to acquire a reproduction signal obtained from a recording part. The recording part includes a recording medium. The reproduction signal includes a first signal corresponding to information recorded in the recording medium. The processor is configured to derive a first output and a second output. The first output is obtained by first information being processed by a first processing model. The first information includes the first signal. The second output is obtained by the first information being processed by a second processing model. The processor is configured to output a result of processing the first information based on a third output. The third output is obtained based on the first output, the second output, and the first information.

Abstract: A memory system connected to a processor is described. The memory system includes a volatile first storage section, a nonvolatile second storage section having a smaller storage capacity than that of the first storage section, and a storage control section that performs control to store data sets in the second storage section. Each of the data sets including data written in the first storage section in response to a write command from the processor, address information indicating a write destination in the first storage section, and address information indicating a write destination in a nonvolatile third storage section to which the data written in the first storage section is to be written back.

Abstract: According to one embodiment, a magnetic memory device includes a conductive member, a first element portion, and a controller. The conductive member includes a first portion, a second portion, and a third portion between the first portion and the second portion. The first element portion includes a first element, a first interconnect, and a first circuit. The first element includes a first magnetic layer, a first counter magnetic layer, and a first nonmagnetic layer. The first counter magnetic layer is provided between the third portion and the first magnetic layer. The first nonmagnetic layer is provided between the first counter magnetic layer and the first magnetic layer. The first interconnect is electrically connected to the first magnetic layer. The first circuit is electrically connected to the first interconnect. The first circuit includes a first switch, a first capacitance element, a first parallel switch, and a first parallel capacitance element.

Abstract: According to one embodiment, a magnetic memory device includes a conductive member, a first element portion, and a controller. The conductive member includes a first portion, a second portion, and a third portion between the first portion and the second portion. The first element portion includes a first element, a first interconnect, and a first circuit. The first element includes a first magnetic layer, a first counter magnetic layer, and a first nonmagnetic layer. The first counter magnetic layer is provided between the third portion and the first magnetic layer. The first nonmagnetic layer is provided between the first counter magnetic layer and the first magnetic layer. The first interconnect is electrically connected to the first magnetic layer. The first circuit is electrically connected to the first interconnect. The first circuit includes a first switch, a first capacitance element, a first parallel switch, and a first parallel capacitance element.

Abstract: A memory system has a first memory to store first-granularity data having a granularity smaller than second-granularity data, the first memory having a memory capacity smaller than a memory capacity of a second memory storing the second-granularity data, a controller to read third-granularity data having a granularity equal to or greater than the first-granularity from the data stored in the second memory, and a data extractor to extract the first-granularity data from the third-granularity data read by the controller and to store the extracted data in the first memory.

Abstract: A memory system has a nonvolatile memory to have a memory capacity equal to or less than a memory capacity of a volatile memory, and store at least a part of data stored in the volatile memory, a first controller to refresh data in the volatile memory, and a second controller to overwrite the nonvolatile memory with data read from the volatile memory in a first period between a second period to refresh data in the volatile memory and a third period to subsequently refresh data in the volatile memory.

Abstract: A memory system connected to a processor is described. The memory system includes a volatile first storage section, a nonvolatile second storage section having a smaller storage capacity than that of the first storage section, and a storage control section that performs control to store data sets in the second storage section. Each of the data sets including data written in the first storage section in response to a write command from the processor, address information indicating a write destination in the first storage section, and address information indicating a write destination in a nonvolatile third storage section to which the data written in the first storage section is to be written back.

Abstract: A cache memory includes cache memory circuitry that is accessible per cache line and a redundant-code storage that stores one or more numbers of first redundant codes to be used for error correction of cache line data stored in the cache memory circuitry per cache line and one or more numbers of second redundant codes to be used for error detection of a part of the cache line data.

Abstract: A memory system has a non-volatile memory used as a first cache memory to be accessed at a higher speed than a main memory, a first translation lookaside buffer that stores address conversion information indicating the conversion of a virtual address issued by a processor into a physical address, and a first control circuitry that stores the address conversion information stored in the first translation lookaside buffer in the non-volatile memory during a power off.

Abstract: A cache memory system includes cache memories of at least one layer, at least one of the cache memories having a data cache to store data and a tag to store an address of data stored in the data cache, and a first address conversion information storage to store entry information that includes address conversion information for virtual addresses issued by a processor to physical addresses and cache presence information that indicates whether data corresponding to the converted physical address is stored in a specific cache memory of at least one layer among the cache memories.

Abstract: According to one embodiment, an information processing method including: detecting by a time information acquiring unit a start and an end of an access of a memory access unit to a target memory, the access of the memory access unit being due to instructions of an instruction issuer, and acquiring by the time information acquiring unit a memory access time being a time from the start of the access till the end of the access; calculating by a computation amount acquiring unit, based on the instructions of the instruction issuer, a computation amount of a computing unit from the start of the access till the end of the access; and evaluating by an evaluation unit, based on the memory access time and the computation amount, computing performance of the computing unit from the start of the access till the end of the access.

Abstract: A memory system has a non-volatile memory of which access speed is electrically controlled, a control circuitry that selects a first region which is a portion of a memory region of the non-volatile memory, and a boost circuit that adjusts an access speed of the first region to be higher than an access speed of a second region different from the first region in the memory region.

Abstract: A memory system has a first cache memory comprising a volatile memory, a second cache memory comprising a non-volatile memory with access speed slower than access speed of the volatile memory, and a reconfiguration control circuitry to switch between a first mode that uses the second cache memory as a cache memory in a lower layer than the first cache memory and a second mode that uses the first cache memory and the second cache memory as cache memories in an identical memory layer.

Abstract: A memory system has a nonvolatile memory to have a memory capacity equal to or less than a memory capacity of a volatile memory, and store at least a part of data stored in the volatile memory, a first controller to refresh data in the volatile memory, and a second controller to overwrite the nonvolatile memory with data read from the volatile memory in a first period between a second period to refresh data in the volatile memory and a third period to subsequently refresh data in the volatile memory.

Abstract: A memory system has a first memory to store first-granularity data haying a granularity smaller than second-granularity data, the first memory having a memory capacity smaller than a memory capacity of a second memory storing the second-granularity data, a controller to read third-granularity data having a granularity equal to or greater than the first-granularity from the data stored in the second memory, and a data extractor to extract the first-granularity data from the third-granularity data read by the controller and to store the extracted data in the first memory.

Abstract: A memory control circuit has a request determination circuitry to determine whether a period without read-out request and write request to an i-th (i being an integer of 1 or more and of n or less, n being an integer of 2 or more) level cache memory among first to n-th level cache memories continues for a first period of time or longer, the i-th level cache memory comprising a first nonvolatile memory, and a power-supply controller to control a power cut-off timing to the i-th level cache memory based on a determination of the request determination circuitry.

Abstract: A memory control circuit has a memory controller that performs access control for a first memory accessed by a first data amount and access control for a second memory of a memory layer equal to the first memory at a read speed lower than a read speed of the first memory by a second data amount larger than the first data amount.

Abstract: A cache memory includes cache memory circuitry that is accessible per cache line and a redundant-code storage that stores one or more numbers of first redundant codes to be used for error correction of cache line data stored in the cache memory circuitry per cache line and one or more numbers of second redundant codes to be used for error detection of a part of the cache line data.

Abstract: A cache memory system has a group of layered memories has two or more memories having different characteristics, an access information storage which stores address conversion information from a virtual address into a physical address, and stores at least one of information on access frequency or information on access restriction, for data to be accessed with an access request, and a controller to select a specific memory from the group of layered memories and perform access control, based on at least one of the information on access frequency and the information on access restriction in the access information storage, for data to be accessed with an access request from the processor, wherein the information on access restriction in the access information storage comprises at least one of read-only information, write-only information, readable and writable information, and dirty information indicating that write-back to a lower layer memory is not yet performed.