Abstract: A cache memory includes a first cache memory that is accessible per cache line, and a second cache memory that is accessible per word, the second cache memory being positioned in a same cache layer as the first cache memory. It is achieved to improve an average access speed to the first cache memory and also to improve access efficiency because of data access per word, thereby reducing power consumption.

Abstract: A cache memory system includes cache memories of at least one layer, at least one of the cache memories having a data cache to store data and a tag to store an address of data stored in the data cache, and a first address conversion information storage to store entry information that includes address conversion information for virtual addresses issued by a processor to physical addresses and cache presence information that indicates whether data corresponding to the converted physical address is stored in a specific cache memory of at least one layer among the cache memories,

Abstract: A memory system has a non-volatile memory used as a first cache memory to be accessed at a higher speed than a main memory, a first translation lookaside buffer that stores address conversion information indicating the conversion of a virtual address issued by a processor into a physical address, and a first control circuitry that stores the address conversion information stored in the first translation lookaside buffer in the non-volatile memory during a power off.

Abstract: A memory system has a non-volatile memory of which access speed is electrically controlled, a control circuitry that selects a first region which is a portion of a memory region of the non-volatile memory, and a boost circuit that adjusts an access speed of the first region to be higher than an access speed of a second region different from the first region in the memory region.

Abstract: A memory system has a first cache memory comprising a volatile memory, a second cache memory comprising a non-volatile memory with access speed slower than access speed of the volatile memory, and a reconfiguration control circuitry to switch between a first mode that uses the second cache memory as a cache memory in a lower layer than the first cache memory and a second mode that uses the first cache memory and the second cache memory as cache memories in an identical memory layer.

Abstract: A high temperature gate valve includes a valve body, a valve element configured to open and close a flow path, and a guide member which is provided in the valve body and guides the valve element in an opening/closing direction. The valve body includes a valve body main portion and a bonnet portion. The valve element slides along the opening/closing direction guided by the guide member. The valve element at a shut-off position blocks the flow path by projecting into the valve body main portion, and at an open position retracts into the bonnet portion. The guide member is divided into a plurality of divided guiding elements along the opening/closing direction, and each of the divided guiding elements are welded to an inside of the valve body.

Abstract: According to one embodiment, an information processing method including: detecting by a time information acquiring unit a start and an end of an access of a memory access unit to a target memory, the access of the memory access unit being due to instructions of an instruction issuer, and acquiring by the time information acquiring unit a memory access time being a time from the start of the access till the end of the access; calculating by a computation amount acquiring unit, based on the instructions of the instruction issuer, a computation amount of a computing unit from the start of the access till the end of the access; and evaluating by an evaluation unit, based on the memory access time and the computation amount, computing performance of the computing unit from the start of the access till the end of the access.

Abstract: A memory control circuit has a request determination circuitry to determine whether a period without read-out request and write request to an i-th (i being an integer of 1 or more and of n or less, n being an integer of 2 or more) level cache memory among first to n-th level cache memories continues for a first period of time or longer, the i-th level cache memory comprising a first nonvolatile memory, and a power-supply controller to control a power cut-off timing to the i-th level cache memory based on a determination of the request determination circuitry.

Abstract: A trace generating unit according to an embodiment of the present invention generates parallel trace information by executing a sequential program code, in case that the above-described sequential program code is parallelized and executed. The sequential program code includes a plurality of processing codes, codes to record a start and an end of the execution for each processing code, and codes to record a start and an end of the execution for each thread. The parallel trace information includes an execution sequence of the threads and an execution sequence of the processing codes for each thread.

Abstract: According to an embodiment, based on task border information, and first-type dependency relationship information containing N number of nodes corresponding to data accesses to one set of data, containing edges representing dependency relationship between the nodes, and having at least one node with an access reliability flag indicating reliability/unreliability of corresponding data access; task border edges, of edges extending over task borders, are identified that have an unreliable access node linked to at least one end, and presentation information containing unreliable access nodes is generated. According to dependency existence information input corresponding to the set of data, conversion information indicating absence of data access to the unreliable access nodes is output.

Abstract: According to an embodiment, a multi-core processor is capable of executing a plurality of tasks. The multi-core processor includes at least a first core and a second core. The first core and the second core are capable of accessing a shared memory area. The first core includes one or more memory layers in an access path to the shared memory area, the one or more memory layers including a local memory for the first core. The second core includes one or more memory layers in an access path to the shared memory area, the one or more memory layers including a local memory for the second core. The local memory for the first core and the local memory for the second core include memories with different unit cell configurations in at least one identical memory layer.

Abstract: A high temperature gate valve includes a valve body, a valve element configured to open and close a flow path, and a guide member which is provided in the valve body and guides the valve element in an opening/closing direction. The valve body includes a valve body main portion and a bonnet portion. The valve element slides along the opening/closing direction guided by the guide member. The valve element at a shut-off position blocks the flow path by projecting into the valve body main portion, and at an open position retracts into the bonnet portion. The guide member is divided into a plurality of divided guiding elements along the opening/closing direction, and each of the divided guiding elements are welded to an inside of the valve body.

Abstract: It is to provide: a generation unit configured to generate one or more reference relationship pairs with reference certainty information of “uncertainty” as presentation information based on first reference relationship information showing whether it is “certain” for the reference data to refer the referenced data or it is “uncertain” for the reference data to refer the referenced data, every reference relationship pair formed with reference data and referenced data; and a conversion unit configured to convert the first reference relationship information into second reference relationship information using an input of a reference relationship for presentation information and reference dependence relationship information showing a dependence relationship between reference relationship pairs.

Abstract: According to an embodiment, based on task border information, and first-type dependency relationship information containing N number of nodes corresponding to data accesses to one set of data, containing edges representing dependency relationship between the nodes, and having at least one node with an access reliability flag indicating reliability/unreliability of corresponding data access; task border edges, of edges extending over task borders, are identified that have an unreliable access node linked to at least one end, and presentation information containing unreliable access nodes is generated. According to dependency existence information input corresponding to the set of data, conversion information indicating absence of data access to the unreliable access nodes is output.

Abstract: A trace generating unit according to an embodiment of the present invention generates parallel trace information by executing a sequential program code, in case that the above-described sequential program code is parallelized and executed. The sequential program code includes a plurality of processing codes, codes to record a start and an end of the execution for each processing code, and codes to record a start and an end of the execution for each thread. The parallel trace information includes an execution sequence of the threads and an execution sequence of the processing codes for each thread.

Abstract: The present invention provides polypeptides that participate in the biosynthesis of the pladienolide macrolide compounds, DNA that encodes these polypeptides and variants of this DNA, transformants that maintain all or a portion of this DNA or variant thereof, and a method of producing the pladienolide macrolide compounds using these transformants. More particularly, it provides an isolated pure DNA that contains at least one region encoding a polypeptide that participates in pladienolide biosynthesis; polypeptide encoded by this DNA; a self-replicating or integrated-replicating recombinant plasmid carrying this DNA; a transformant maintaining this DNA; and a method of producing a pladienolide, characterized by culturing this transformant on culture medium and collecting pladienolide from this culture medium.